Sr. or MTS DFT Engieer

RecruiterAMD

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DFT Engineer

RESPONSIBILITIES:

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Participate in SOCfull Chip DFT feature and architecture definition

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Responsible for DFTspecification generation and review

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Implement SOC DFTfunction including SCAN, Boundary SCAN, MBIST, Analog Macro test logic.

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Perform verificationon all DFT structures

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Generate DFT relatedtiming constraints and work with PD team for timing closure

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Generate and verifyDFT structural patterns and functional patterns

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Participate in ATEbring-up and debug the DFT patterns on ATE

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Design and implementother DFX (debug, characterization, yield etc) logics

REQUIREMENTS:

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BS in EE &CS.  MS preferred, with 4+ years experience.

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Hands on workingexperience on ASIC DFT design and verification

        Familiar with entire ASIC design flow

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Experience with microprocessor design a big plus

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Should have strongproblem solving skills
Good English hearing, speaking, reading and writing capabilities

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Good communicationskills