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本帖最后由 空白MAX 于 2018-11-17 18:26 编辑
我用的是http://bbs.eetop.cn/thread-839463-1-1.html的虚拟机然后加了UVM变量,准备试一下张强书里的源码能不能跑
出现错误
刚开始接触linux很多都不懂,是我环境变量设定的不对还是别的问题?我改用以下命令后出现了新的问题,请问这是什么情况呢?
[IC@IC 2.5.2]$ vcs -sverilog +incdir+$UVM_HOME/src top_tb.sv
Chronologic VCS (TM)
Version I-2014.03 -- Sat Nov 17 17:34:13 2018
Copyright (c) 1991-2014 by Synopsys Inc.
ALL RIGHTS RESERVED
This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.
Parsing design file 'top_tb.sv'
Parsing included file '/home/IC/uvm-1.1d/src/uvm_macros.svh'.
Parsing included file '/home/IC/uvm-1.1d/src/macros/uvm_version_defines.svh'.
Back to file '/home/IC/uvm-1.1d/src/uvm_macros.svh'.
Parsing included file '/home/IC/uvm-1.1d/src/macros/uvm_message_defines.svh'.
Back to file '/home/IC/uvm-1.1d/src/uvm_macros.svh'.
Parsing included file '/home/IC/uvm-1.1d/src/macros/uvm_phase_defines.svh'.
Back to file '/home/IC/uvm-1.1d/src/uvm_macros.svh'.
Parsing included file '/home/IC/uvm-1.1d/src/macros/uvm_object_defines.svh'.
Back to file '/home/IC/uvm-1.1d/src/uvm_macros.svh'.
Parsing included file '/home/IC/uvm-1.1d/src/macros/uvm_printer_defines.svh'.
Back to file '/home/IC/uvm-1.1d/src/uvm_macros.svh'.
Parsing included file '/home/IC/uvm-1.1d/src/macros/uvm_tlm_defines.svh'.
Parsing included file '/home/IC/uvm-1.1d/src/tlm1/uvm_tlm_imps.svh'.
Back to file '/home/IC/uvm-1.1d/src/macros/uvm_tlm_defines.svh'.
Back to file '/home/IC/uvm-1.1d/src/uvm_macros.svh'.
Parsing included file '/home/IC/uvm-1.1d/src/macros/uvm_sequence_defines.svh'.
Back to file '/home/IC/uvm-1.1d/src/uvm_macros.svh'.
Parsing included file '/home/IC/uvm-1.1d/src/macros/uvm_callback_defines.svh'.
Back to file '/home/IC/uvm-1.1d/src/uvm_macros.svh'.
Parsing included file '/home/IC/uvm-1.1d/src/macros/uvm_reg_defines.svh'.
Back to file '/home/IC/uvm-1.1d/src/uvm_macros.svh'.
Parsing included file '/home/IC/uvm-1.1d/src/macros/uvm_deprecated_defines.svh'.
Back to file '/home/IC/uvm-1.1d/src/uvm_macros.svh'.
Back to file 'top_tb.sv'.
Error-[SV-LCM-PND] Package not defined
top_tb.sv, 4
$unit, "uvm_pkg::"
Package scope resolution failed. Token 'uvm_pkg' is not a package.
Originating module '_vcs_unit__1'.
Move package definition before the use of the package.
Parsing included file 'my_if.sv'.
Back to file 'top_tb.sv'.
Parsing included file 'my_transaction.sv'.
Error-[SE] Syntax error
Following verilog source has syntax error :
"my_transaction.sv", 4: token is 'uvm_sequence_item'
class my_transaction extends uvm_sequence_item;
^
2 errors
CPU time: 2.698 seconds to compile
知道咋回事了,还是要写makefile定义编译顺序 |
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