【上海】莱迪思半导体招聘资深模拟电路设计工程师--Serdes方向

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莱迪思半导体(Lattice Semiconductor)是一家专业从事FPGA设计和销售在NASDAQ上市的美国公司。公司产品广泛用于工业控制，通信，和消费类产品领域。莱迪思半导体（上海）有限公司成立于1993年，办公地点位于漕河泾科技绿洲，是在中国的研发中心。由于业务需要，目前公司招聘资深模拟电路设计工程师，主要从事高速Serdes IP开发，具体信息请看下面岗位介绍和要求。公司提供有竞争力的薪资待遇，良好的工作学习氛围让你和公司一道成长。需要候选人有扎实的模拟电路设计基础和一定的相关领域经验，以及对新技术新知识强烈的学习动力。如果你是合适的人选，请把简历寄到： hr.lsh@latticesemi.com

Job Description:
Lattice Semiconductor is seeking a Senior analog design engineer to focus on serdes and high speed analog/mixed signal IP development.
This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn and grow as the important team member of Serdes IP development team.
The Senior Analog Design Engineer will apply his/her IP design skills to develop Serializer/Deserilizer (SerDes)  IP for various FPGA products in Lattice. The successful candidate will work closely with leader in analog IP team and other silicon development teams to develop high quality and cost effective FPGA products in advanced CMOS process nodes.
This position is ideal for analog design engineer with certain experience to explore further opportunity which could improve his/her high speed design technical knowledge to a higher level. Also it offers very good chance to candidate to have deep understanding how a FPGA silicon product is developed.

Responsibilities:
• Develop novel analog/mixed signal circuit techniques and architecture to facilitate high bandwidth (muti-gigabit per second) serial communication network and links. Focus on 5Gbps~10Gbps Serializer/Deserializer (SerDes) transceiver IP for multiple protocols serial link application, including PCIe, USB, Display-port, SDI, HDMI etc.
• Candidate will focus on important building blocks design for complex Serdes IP system, such as PLL, Clock Data Recovery (CDR), equalizer, serializer, deserializer, transmitter, termination, IO/ESD etc.
• Development task starts from specifciation to final IP release. Detail work includes design spec, circuit architecture and implementation, prelayout and postlayout simulation,  behavior modeling, IP integration and silicon bring up and debug.

Required Skills:
• Demonstrated strong analog or mixed signal IP design skills in high speed connectivitity product development
• Solid knowledge in analog circuit, signal processing theory and semiconductor device physics
• Hands on skills in circuit desgin, simulation, verilog and verilog-A behavior modeling
• Familiar with main stream EDA tools in analog  mixed signal design
• Strong  problem analysis and debug skill
• Good oral and writing English communication skill
• Ability to multi-tasks and set priorites with tight schedule

Experience  Requirement:
• At least 5 years of experience in analog or  mixed signal IP development under advanced CMOS process node (65nm and below)
• Experience with one or more following areas: PLL, CDR, equalizer, transmitter, IO
• Experience working with layout team together and guide layout optimization to achieve high quality layout
• Experience in product tape out and  silicon bring up/debug
• Experience working in dynamic, fast-paced company environment
• MS or PhD Degree in Electrical Engineering with an emphasis in analog or mixed signal design