上海KT人才-招聘 综合 人才...合适的进~!

dolphinsrf

职位描述：
职位要求：
Must master chip-level synthesis using Design Compiler.Has a well understanding of timing constraints,clocking and synthesis strategy.Well understand Verilog RTL code and can work with RTL logic design engineer to address RTL synthesizability.

Must master chip-level DFT including scan specification,scan chain insertion,BSD insertion,ATPG pattern generation/coverage and pattern simulation. Hand-on experience on how to improve test coverage and reduce tester time by test vector compression.Understand deep submicron test strategies such as path delay test,transition test,bridge test and IDDQ test.Work with RTL logic design engineer to address design testability.

Must master chip-level STA using PrimeTime/PrimeTime-SI. Work closely with RTL logic design engineer to write chip-level timing constraints.Address timing closure problems with RTL design engineer in synthesis stage and place & route engineer in physical design stage.Perform sign-off timing/SI closure and generate SDF for verification engineer.

Understand how to perform chip/block power analysis and optimization.

Proficient in scripting languages (Perl/Tcl)

Experience with deep sub-micron technology.90nm is a big plus.

Must be self-motivated,a team-player with good work ethics and problem solving skills

职责描述：
The candidate will primarily work on top or block level synthesis,DFT,and timing/SI closure,logic equivalence and power analysis.Another primary responsibility for this candidate is to work with RTL logic design engineer closely to make sure RTL code can be physically implemented given technology and library.The candidate may also assist physical design team on floor planning,place and route and more.



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