2007 CICC: 15, 16

casdvo · 发表于 2007-9-29 05:41:17

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Session 15 – CMOS Scaling and Technology Implications

Cedar Ballroom, Tuesday Morning, September 18

Chair:  David Sunderland

Co-Chair:  Jordan Lai

This session of invited papers addresses important issues related to maintaining Moore’s Law scaling beyond 45nm, focusing on device technology, package technology, reliability and physical analysis.

8:25 am

Introduction

15.1  -  8:30 am

Reliability Trends with Advanced CMOS Scaling and the Implications for Design (INVITED PAPER)

J. McPherson, Texas Instruments

15.2  -  9:20 am

Evolution of CMOS Technology at 32 nm and Beyond (INVITED PAPER)

G. Shahidi, IBM

15.3  -  9:45 am

High-K/Metal Gate Technology: A New Horizon (INVITED PAPER)

M. Khare, IBM

10:10 am - BREAK

15.4  -  10:25 am

Revolutionary NanoSilicon Ancillary Technologies for Ultimate-Performance Gigascale Systems (INVITED PAPER)

M. Bakir, B. Dang and J. Meindl, Georgia Institute of Technology

15.5  -  11:15 am

Reverse Engineering in the Semiconductor Industry (INVITED PAPER)

R. Torrance and D. James, Chipworks, Inc.

Session 16 – Signal and Data Processing

Oak Ballroom, Tuesday Afternoon, September 18

Chair:  Charles Thomas

Co-Chair:  Ram Krishnamurthy

This session explores new signal and data processing integrated circuits for a diverse reange of applications including medical devices, video processing and high speed communications.

2:00pm

Introduction

16.1  -  2:05 pm

Cochlear Implant Signal Processing ICs (INVITED PAPER)

B. Swanson, M. Goorevich, T. Nygard, Cochlear Ltd., E. Van Baelen, K. Van Herck, Cochlear Technology Center, and M. Janssens, NXP

16.2  -  2:55 pm

An 81.6 GOPS Object Recognition Processor Based on NoC and Visual Image Processing Memory

D. Kim, K. Kim, J.-Y. Kim, S. Lee and H.-J. Yoo, KAIST

16.3  -  3:20 pm

A Cost-effective Digital Front-End Realization For 20-bit ΣΔ DAC in 0.13µm CMOS

R. Chen, L. Liu and D. Li, Tsinghua University

3:45 pm - BREAK

16.4  -  4:00 pm

A 0.25µm 0.92mW per Mb/s Viterbi Decoder Featuring Resonant Clocking for Ultra-Low-Power 54Mb/s WLAN Communication

F. Carbognani, S. Haene, M. Arrigo, C. Pagnamenta, F. Buergin, N. Felber, H. Kaeslin and W. Fichtner, ETH Zurich

16.5  -  4:25 pm

A High-Throughput Maximum a posteriori Probability Detector

R. Ratnayake, G.-Y. Wei, Harvard University, A. Kavcic, University of Hawaii

16.6  -  4:50 pm

A 3.3-Gbps Bit-Serial Block-Interlaced Min-Sum LDPC Decoder in 0.13µm CMOS

A. Darabiha, A. Chan Carusone and F. Kschischang, University of Toronto