Tab | Job Title | Key words | Link |
武汉IP研发 | ASIC Digital Design Engr,
| ASIC Design/Verification for Embedded Vision/Convolution Neural Network IP(RTL, UVM, SystemVerilog, Computer Architecture) | https://sjobs.brassring.com/TGnewUI/Search/Home/Home?partnerid=25235&siteid=5359#jobDetails=1373739_5359 |
武汉IP研发 | ASIC Digital Design Engr | IP/ASIC digital design/verification, RTL, UVM/VMM | https://sjobs.brassring.com/TGnewUI/Search/Home/Home?partnerid=25235&siteid=5359#jobDetails=1381436_5359 |
武汉IP研发 | Supv , ASIC Digital Design | IP/ASIC digital design/verification\RTL、Logical design、STAT、MIPI | https://sjobs.brassring.com/TGnewUI/Search/Home/Home?partnerid=25235&siteid=5359#jobDetails=1337328_5359 |
武汉IP研发 | ASIC Digital Design Engr | Digital design, Serdes IP, Accept FY18 Fresh Master pipeline | https://sjobs.brassring.com/TGnewUI/Search/Home/Home?partnerid=25235&siteid=5359#jobDetails=1313431_5359 |
武汉IP研发 | ASIC/Layout Design Engr,
| IP/ASIC, layout, mixed-signal | https://sjobs.brassring.com/TGnewUI/Search/Home/Home?partnerid=25235&siteid=5359#jobDetails=1389542_5359 |
武汉IP研发 | ASIC Digital Design Engr,
| IP/ASIC digital design/verification, Timing constraints and floorplan-aware synthesis. DFT, ATPG Validation | https://sjobs.brassring.com/TGnewUI/Search/Home/Home?partnerid=25235&siteid=5359#jobDetails=1387295_5359 |
武汉IP研发 | ASIC Digital Design Engr, Sr | IP/ASIC digital design/verification, CPU, architecture | https://sjobs.brassring.com/TGnewUI/Search/Home/Home?partnerid=25235&siteid=5359#jobDetails=1382895_5359 |
武汉IP研发 | ASIC Digital Design Engr | Digital design, SRAM IP, embedded memory, Accept FY18 Fresh Master pipeline | https://sjobs.brassring.com/TGnewUI/Search/Home/Home?partnerid=25235&siteid=5359#jobDetails=1313085_5359 |
武汉IP研发 | ASIC Digital Design Engr, | IP/ASIC design or verification experience; SRAM IP, embedded memory; Memory IP; Accept FY18 Fresh Master pipeline | https://sjobs.brassring.com/TGnewUI/Search/Home/Home?partnerid=25235&siteid=5359#jobDetails=1313044_5359 |
武汉IP研发 | Mgr , ASIC Digital Design | IP/ASIC digital design/verification, Team management, Timing constraints and floorplan-aware synthesis. DFT, ATPG Validation | https://sjobs.brassring.com/TGnewUI/Search/Home/Home?partnerid=25235&siteid=5359#jobDetails=1332922_5359 |
武汉IP研发 | Analog Design Engr,
| IP/ASIC, layout, mixed-signal, top-sim | https://sjobs.brassring.com/TGnewUI/Search/Home/Home?partnerid=25235&siteid=5359#jobDetails=1389548_5359 |
武汉IP研发 | Analog Design Engr, Sr
| IP/ASIC, A&MS, mixed-signal, analog | https://sjobs.brassring.com/TGnewUI/Search/Home/Home?partnerid=25235&siteid=5359#jobDetails=1389550_5359 |
武汉IP研发 | Quality Engineer, Sr
| Quality Engineer, ISO 9001/Semiconductor | https://sjobs.brassring.com/TGnewUI/Search/Home/Home?partnerid=25235&siteid=5359#jobDetails=1387008_5359 |
武汉安全软件技术顾问 | Applications Engineer, Sr | Java/ web application security/ C#, .NET | https://sjobs.brassring.com/TGnewUI/Search/Home/Home?partnerid=25235&siteid=5359#jobDetails=1335367_5359 |