AI研发公司北京上海芯片设计全定制前端综合芯片算法等职位招聘

daisyyang

AI研发公司北京上海芯片设计全定制前端综合芯片算法等职位招聘，有兴趣联系，电话和微信18163979512，邮箱daisy.yang@hibrhr.com

芯片设计  北京/上海

岗位职责

1.             Participate in DLA（Deep Learning Accelerator）, GPU or other SOC IP design for all frontend phase

2.             Specification define

3.             RTL implementation

4.             Analysis and optimization for performance

5.             Analysis and optimization for power

6.             Analysis and optimization for timing

7.             Design flow: lint/synthesis/sta/formal check

8.             Silicon debugging

任职条件

1.
MS with 5+ or 3+ years of experience in ASIC design

2.
Experience with DLA （Deep Learning Accelerator）or GPU related IPs design are highly desirable

3.
Experience with CPU related IPs design are highly desirable

4.
Experience with PCIE, CCIX or other high speed interface IPs design are highly desirable

5.             Experience with all phases of frontend architecture, design and validation

6.             RTL Coding, design reviews, SYN, CDC, FEV

7.             Demonstrated work experience with timing analysis, area and power optimizations, performance analysis, debug ability, ECOs, and post-silicon debug

8.             Excellent knowledge of Verilog and popular EDA simulation & implementation tools

9.             Good experience in scripting languages like Perl, Unix shell or similar languages

ASIC算法工程师  北京

职位概述

岗位职责 1、对所用到的算法进行建模，在芯片实现之前评估最终能实现的性能/功耗等指标；

2、根据系统性能功耗和成本要求，优化架构设计；

3、解决芯片设计实现过程中的技术问题，确保关键规格的达成；

4、负责芯片核心算法的RTL实现及ASIC前端的设计工作。

任职条件 1、 微电子集成电路专业，或计算机通讯等相关专业，硕士及以上学历；

2、 能够熟练使用C语言，或者matlab进行算法建模；

3、 扎实的数字电路设计基础，精通verilog语言。能够将复杂算法映射成RTL；

4、 对安全加解密算法，数字签名算法有深入研究的优先；

5、 有ASIC前端开发经验的优先；

6、 有software/Firmware/算法开发经验者优先。

Digital Implementation Engineer    北京

职位概述

岗位职责

•
Responsible for digital logic synthesis, STA, formal verification, DFT, power analysis, RTL design quality checking.

•
Responsible to develop timing constraint and low power design constraint

•
Responsible to co-work with physical design team for timing closure

•
Responsible to optimize digital frontend flow qualification

•
Responsible to develop signoff methodology for standard PVT and non-standard PVT.

•
Responsible to block level digital implementation.

任职条件

•
Major in CS, EE or related, MSEE required

•
2+ years working experience is preferred.

•
Deep understanding of timing signoff flow.

•
Good knowledge of digital logic design, synthesis, formal verification, etc.

•
Good experience with Design compiler, Prime time and Formality/Conformal LEC, spyglass/0in.

•
Experience of DFT/MBIST is a plus.

•
Hands-on experience in full-chip/block level, place and route, floor planning, power and clock optimization is a plus.

•
Implementation experience on 28nm or above process node is plus.

•
Familiar with common UNIX utility such as Shell, Perl, TCL, good scripting ability.

•
Good English communication skills.

•
Good initiative and motivation in a challenging environment.

全定制芯片设计工程师    北京/上海

职位概述

岗位职责

High performance, low power, small area custom digital circuit design for processors·

Circuit architecting, simulation and characterization of custom design circuit.                           

1. Transistor level function verification.

2. Participating in building CAD flow for circuit design.

3. Layout floor planning and supervision.

任职条件

1. BSEE minimum, MSEE preferredwith 1-5 years of working experience;

2. Strong background in deep submicron CMOS process and device.

3. Good knowledge in high speed digitalcircuit design techniques.

4. Experience in circuit simulation, schematic capture and layout verification CAD tools.

5. Must be a team player with effective written and verbal communication skills.

6. Quick learner and work independently.

ASIC Flow工程师
北京/上海

职位概述

1.
负责module/SOC level SDC结构设计，协同RTL Designer完成SDC分析、维护。

2.
负责SDC验证 flow建立与维护。

3.
参与Synthesis/Formal/STA等前端flow环境建立与优化。

4.
配合designer、后端完成sdc/timing分析与收敛。

岗位职责

1.
负责module/SOC level SDC结构设计，协同RTL Designer完成SDC分析、维护。

2.
负责SDC验证 flow建立与维护。

3.
参与Synthesis/Formal/STA等前端flow环境建立与优化。

4.
配合designer、后端完成sdc/timing分析与收敛。

任职条件

1.
计算机、电子、半导体相关专业本科及以上学历，2年及以上相关工作经验。

2.
熟练掌握Synopsys SDC/Synthesis/Formal/STA工具和流程，具有较强的环境建立能力。

3.
对module/SOC SDC架构设计、SDC与综合/STA flow的整合有深入理解和项目经验。

4.
对DCG综合优化与后端一致性、STA signoff有深入理解与实际经验。

5.
具有较丰富的28nm及以下制程ASIC前端flow相关经验，至少一次成功流片经验。

6.
熟练掌握tcl/perl/shell/Makefile等语言，能够独立建立前端flow并进行优化。

7.
良好的沟通能力，快速学习实践以及团队合作能力。