北京上海 DFT职位紧急招人

daisyyang

北京上海DFT职位招聘，欢迎咨询，欢迎推荐，电话和微信：18163979512，邮箱daisy.yang@hibohr.com

DFT工程师：
Job description
Perform and/or lead various DFT tasks for the creation of SOC chips. The main areas of focus will be to architect, develop and optimize structured test solutions using DFT insertion and ATPG tools as well as BIST for memories, etc. He will be responsible for architecting and integrating DFT structures into RTL and netlists to deliver reliable, efficient and high quality manufacturing test coverage.

Key Responsibilities:
• Architect DFT strategies for complex SOC designs
• Generate and insert Scan, Memory BIST, Boundary Scan, Test Compression etc.
• Generate ATPG vectors for stuck-at, delay fault and other types
• Determine, analyze and enhance fault coverage to achieve target test quality
• Interface with ATE test engineer

Requirements:
•BS/MS in Electrical or Computer Engineering with 5+ years’related experience designing DFT for SOCs
•Expert level knowledge of DFT including scan, boundary scan, BIST, fault models and ATPG
•Strong working knowledge of SOC design and design methodology
•Skill and efficiency in scripting using common UNIX scripting languages such as TCL, Perl, csh
•Excellent RTL and gate level debug skills
•Strong experience with Verilog RTL design and simulation
•Desirable: Previous use/experience with ATE
•Desirable: Formal analysis / STA Experience