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Responsibility: ·
Develop micro-architecture for GPU blocks based on architecturalrequirement. ·
Develop RTL code for GPU blocks in Verilog HDL and make surefunctional correct and reusable for different configuration. ·
Synthesis and deliver netlist that meeting timing, area and powerrequirement. Help PD on the floorplanning and close timing. ·
Analyze gating efficiency report to improve RTL quality Requirement: ·
MS degree of EE with 5+ years working experience in ASIC Company. ·
Expert of Verilog RTL design and has experience of large digitalASIC project. ·
Familiar with front-end EDA tools and flows. ·
Familiar with C/C++ programming and unix/linux and scripts (tcl,perl etc.) ·
Fluent English on talking, presentation and writing documents. ·
Work is performed with limited supervision. Strong sense of taskscheduling and deliver on time as predetermined milestones committed tomanager. ·
Can solves complex, novel and non-recurring problems; initiatessignificant changes to existing processes/methods and leads development andimplementation ·
Possesses specialized knowledge of Computer architecture andcomputer arithmetic (a plus) ·
Possesses specialized knowledge of Computer graphic knowledge (aplus)
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