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美满电子科技(南京)有限公司
Responsibility: 1. Implementing from Synthesis to GDSII that includessynthesis/Scan Insertion/P&R/ timing signoff/physical signoff and allvariety check for Higher QoR 2. Power fixing based on power analysis result 3. Develop methodologies to make daily work more efficient 4. Cooperate with designers on RTL issues which relative tobackend timing closure and congestion solve. 5. Debugging the flow to make it advance.
Job Requirements: Education& Qualifications: 1. Candidate is preferred to be MSEE with minimum of 3 years, orBSEE with minimum of 5-year experience in digital ASIC/SOC Physical design
Experience: 1. Have DRC/LVS/ERC/Antenna debugging skills 2. Knows Cadence/Synopsys Implement flow such as DCT/ICC orGenus/Innovus flow. 3. Good programming skill. 3. Understanding the DFT concept w/ scan chain insertion. 4. Knows low power methodologies for BE implement. 5. Capable of writing Tcl or Perl. 6. Familiar with synthesis, static timing analysis,Understanding timing signoff w/ Primetime or Tempus. 7. Familiar with RTL Design in Verilog is a plus. 8. Self-motivated team worker, good verbal and written communicationskills in English.
工作地点:南京
有意向的请发简历到邮箱:254188191@qq.com
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