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本帖最后由 igovip 于 2018-3-16 15:41 编辑
成都海光招聘SOC设计/集成工程师 (Senior/Staff), 感兴趣的朋友请发简历至my_dipper@outlook.com,机会不错(特别是对打算从北上深回成都的朋友),欢迎邮件咨询
Job Title: ASIC Design/Integration Engineer (Senior/Staff)
Description:
- SoC top level design
- Working with IP vendor (internal/external) for RTL deliver, quality and analyze integration issues
- Working with physical design team for timing closure
- SOC level LEDA, CDC check
- SOC level sdc/constraints generation, formal/lec check- SOC level timing analysis and low power check
- Chip quality sign-off
Qualifications:
Must have:
- minimum 3+/6+ years of ASIC design or integration experience
- proficient in Verilog HDL
- solid working knowledge with front-end ASIC design flow and EDA tools (Verdi,Formality/LEC, DC, PT, Spyglass, etc.)
- good team work spirit
Nice to have:
- familiar with low power flow(upf,vsi check, etc.)
- working knowledge in DFT construction and integration |