Cadence Principal / Lead Application Engineer –前端验证热招中

kengteng

Cadence Principal / LeadApplication Engineer –前端验证热招中

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If you have interest, PLS send your update CV to job_china@cadence.com

Principal / Lead Application Engineer (Front-end Verification)

Location:Shanghai / Beijing

PositionDescription:

- Workclosely with the Sales team to identify and scope opportunities for Cadence SoC Verification solution, simulation Emulationand Acceleration products.

- Plan,execute and manage key technical evaluations and benchmark with existing andpotential customers.

- Train,ramp-up and accompany customer project.

- Conductbasic and advanced trainings, presentations and demos as necessary.

- Providingtechnical expertise to address clients’ queries, which need expert involvement.

- Alignedclosely with corporate engineering and sales/marketing team on customerrequirement for product direction/improvement.

PositionRequirements:         

- 4~8 years’ experience in the following areas:

- Design experience in Verilog/VHDL for IP orSoC chip level.

- HW verification with knowledge of System Verilog/VHDLand HDL simulators

- FPGAprototyping project experience

- Experiencewith hardware emulator or accelerator is a big advantage

- Advanced Verification Methodology like UVM is a plus

- Knowledgeof Unix and Linux is highly desired

- Strongverbal and written communication skills in English

- Strongteamwork skills with good human relationship