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[招聘] 2017/12_OPEN职位_瑞雪丰年_上海/北京/苏州

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发表于 2017-12-5 22:40:36 | 显示全部楼层 |阅读模式

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瑞雪丰年,在等待年终奖的同时也可以为自己新的一年规划规划了! AMD的职位或许某个是为你专设的。
AMD会带你走到最前沿的技术阵地,给你一个发挥最大技术潜力的平台。优秀的你,还等什么?

AMD(超威半导体)2017最新open的职位也出炉了,数字ASIC前后端,design、验证、软件驱动开发、platform等。
PS:招聘只面向社招
公司内部推荐,成功率会高些哦。大家都是工程师,对工作的切入点也会更准确,并且可以指导简历修整,突出个人优势,让个人特长和职位需求更好的match,实现共赢哟。有兴趣的童鞋们可以把简历直接发邮件到我的邮箱 : amd_cdc@163.com或者加我QQ1756384832。有任何关于这边面试、公司文化、工作环境、职业发展的问题都欢迎交流,希望能有效提高你应聘的目的性和面试的成功几率,更希望你能赢得能发挥你个人优势的职位。


@上海:
1.  PMTS/SMTS/MTS/Sr Machine/ Deep Learning Software engineer  Urgent
2.  PMTS/SMTS/MTS/Sr Machine/ Deep Learning Software engineer  Urgent
3.  MTS ASIC/ Layout Design Engineer-Feint  Urgent
4.  ASIC/ Layout Design Engineer 2 - DFX   Urgent
5.  Sr. /MTS ASIC/Layout Design Engineer (Graphics Performance Verification)  Urgent
6.  PMTS/SMTS/MTS/Sr PD Engineer  Urgent
7.  Sr. Manager/ PMTS ASIC Design Urgent
8.  Program Manager 2 Urgent
9.  Sr./MTS CAD Engineer Urgent
10. Sr./MTS BIOS Engineer   Urgent
11. Senior Memory Control Diagnostic Firmware Engineer Urgent
12. Senior Multimedia Diagnostic Firmware Engineer Urgent

13. Virtulization technical application engineer( Data center group)
14. SMTS/MTS/Sr. DV Engineer
15. MTS Software Dvpmt Eng OpenGL
16. Software Engineer2
17. SMTS/MTS/Sr. Systems Design Eng-Platform
18. Sr./MTS ASIC Design Verification Engineer (Graphics IP)  
19. Sr./MTS ASIC Design Verification Engineer (3D Graphics)
20. MTS ASIC Design Verification Engineer (Front-End Engineer - Graphics)
21. SMTS/ MTS ASIC Design Engineer – Graphics IP   
22. SMTS/ PMTS Design verification Engineer  
23. Sr. /MTS ASIC/Layout Design Engineer (Graphics Performance Analysis)
24. Sr. /MTS Methodology Verification Engineer
25. Sr./MTS Front-end design Engineer (CAD)
26. MTS ASIC Design Engineer - Memory Controller
27. SMTS Front End Integration Engineer
28. Sr. Validation Engineer
29. MTS Physical Design Engineer
30. Goverment and Public Affairs Sr. Manager
31. MTS BIOS/Firmware Engineer
32. MTS Product Application Eng.
33. SMTS Quality Engineer
34. SMTS Firmware Engineer
35. Program Manager 1

@北京:
1.  SMTS/MTS/ Sr. Physical Design Engineer
2.  MTS / Sr. DV Engineer
3.  MTS / DV Engineer

@苏州:
1.  MTS Packaging Engineer  Urgent
 楼主| 发表于 2017-12-7 22:33:15 | 显示全部楼层
 楼主| 发表于 2017-12-9 11:50:49 | 显示全部楼层
 楼主| 发表于 2017-12-12 23:17:10 | 显示全部楼层
如果你对AMD感兴趣,可以了解一下AMD
 楼主| 发表于 2017-12-17 19:17:13 | 显示全部楼层
 楼主| 发表于 2017-12-19 22:53:13 | 显示全部楼层
 楼主| 发表于 2017-12-24 23:02:38 | 显示全部楼层
本帖最后由 amd_srdc 于 2017-12-24 23:03 编辑

Merry Xmas
 楼主| 发表于 2017-12-25 23:18:57 | 显示全部楼层
 楼主| 发表于 2018-1-22 23:12:11 | 显示全部楼层
特别推荐:  SOC Integration Team (成功率很高)
急招 SMTS/MTS/Sr ASIC Layout Design Engineer - FEINT  Urgent

Job Responsibilities:
•        Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
•        Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology.
Job Requirements:   
•        Familiar with Verilog RTL design and has experience of large digital ASIC project.
•        Familiar with front-end EDA tools and flows (Design compiler, PrimeTime, Conformal,Verde)
•        Familiar with unix/linux and scripts (tcl, perl etc.)
•        Fluent English on talking, presentation and writing documents.
•        Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
 楼主| 发表于 2018-1-22 23:14:24 | 显示全部楼层
特别推荐: SOC Integration Team (成功率很高)
急招: SMTS/MTS/Sr ASIC Layout Design Engineer - FEINT (上海)

Job Responsibilities:
•        Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
•        Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology.
Job Requirements:   
•        Familiar with Verilog RTL design and has experience of large digital ASIC project.
•        Familiar with front-end EDA tools and flows (Design compiler, PrimeTime, Conformal,Verde)
•        Familiar with unix/linux and scripts (tcl, perl etc.)
•        Fluent English on talking, presentation and writing documents.
•        Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
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