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发表于 2018-1-22 23:12:11
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特别推荐: SOC Integration Team (成功率很高)
急招 SMTS/MTS/Sr ASIC Layout Design Engineer - FEINT Urgent
Job Responsibilities:
• Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
• Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology.
Job Requirements:
• Familiar with Verilog RTL design and has experience of large digital ASIC project.
• Familiar with front-end EDA tools and flows (Design compiler, PrimeTime, Conformal,Verde)
• Familiar with unix/linux and scripts (tcl, perl etc.)
• Fluent English on talking, presentation and writing documents.
• Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager. |
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