【英伟达Nvidia上海社招】Sr/ DFT Engineer

Nvidia_Staffing

简历投递邮箱： nahu@nvidia.com咨询电话: 021-61041985

Design-for-TestEngineering at NVIDIA works on groundbreaking innovations involving craftingcreative solutions for DFT architecture, verification and post-siliconvalidation on some of the industry's most complex semiconductor chips.

What you’ll be doing:

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You'll be responsible for DFTplanning, DFT implementation, DFT verification and silicon bring up at IP orfullchip level for all of NVIDIA's semiconductor products

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In addition, you will have chance toimprove DFT design, architecture and flow

What we need to see:

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Familiar with Verilog and ASIC design

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Demonstrated knowledge and expertisein defining Scan test plans, BIST including memories and IOs, ATPG, faultmodels and fault simulation

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Excellent analytical skills inverification and validation of test patterns and logic on complex andmulti-million gate designs using vendor tools

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Good exposure to cross-functionalareas including RTL & clocks design, STA, place-n-route and power, toensure we are making the right trade-offs

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Experience in silicon debug andbring-up on the ATE with an understanding of pattern formats, failureprocessing and diagnostics

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Strong programming and scriptingskills in Perl, Python or Tcl desired

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Extraordinary written and oralcommunication skills in English with the curiosity to work on rare challenges