北京南5环招聘数字设计项目经理等人才

hamy

招聘信息：地点：北京南5环，薪资open，欢迎来撩~   


职位  1： ASIC Design Project Leader /数字设计项目经理  


工作职责：   
1.Responsible for whole chip development and leading digital team to develop digital blocks according to product specifications;   
2.Logic design & implementation by Verilog on module level, and chip integration;  
3.Design synthesis, CDC checking, timing analysis, DFT and ATPG;   
4.Work closely with analog and backend engineer for chip physical design and tape-out;  
5.Work closely with application engineer for chip bring-up, debug and solve problem;  
6.Good IC verification skills and solid logic and circuit design knowledge, good communication and problem solving skills;  
7.Interest of IC project management. Good knowledge of Perl and shell programming would be an added advantage.  


职位要求：   
1.Bachelor, Master or above in Electronic, Communications, Microelectronics Engineering and Computer Science;  
2.At least 8+ years of experience in digital design based on high-level languages (preferable Verilog), with knowledge of ASIC FE design flow, including coding, simulation, verification, synthesis, DFT and STA;  
3.Familiar with EDA tools from Synopsis, Cadence or Mentor, like NC-Verilog, VCS, DC and Prime Time;  
4.Familiar with video/image process algorithm would be an added advantage;  
5.Experience of chip volume production;  
6.Familiar with FPGA prototyping development;  
7.Familiar with mixed signal or SoC design is better;  
8.Good written and oral English communication skills.  




职位  2：  Sr. ASIC Design Engineer / 高级数字设计工程师  


工作职责：   
1.   Logic design & implementation by Verilog on module level, and block integration;  
2.   Design synthesis, CDC checking, timing analysis, DFT and ATPG;   
3.   Work closely with application engineer for chip bring-up, debug and solve problem;  
4.   Good IC verification skills of logic and circuit design, good communication and problem solving skills;  
5.   Experience with verification tools such as System Verilog, UVM or System C/Testbuilder, etc.   
6.   Good knowledge of Perl and shell programming would be an added advantage.  


职位要求：   
1.   Bachelor, Master or above in Electronic, Communications, Microelectronics Engineering and   
      Computer Science;  
2.   At least 5+ years of experience in digital design based on high-level languages (preferable   
      Verilog), with knowledge of ASIC FE design flow, including coding, simulation,      
      verification, synthesis, DFT and STA;  
3.   Familiar with EDA tools from Synopsis, Cadence or Mentor, like NC-Verilog, VCS, DC and   
      Prime Time;  
4.   Familiar with video/image process algorithm would be an added advantage;  
5.   Familiar with FPGA prototyping development;  
6.   Familiar with mixed signal or SoC design is better;  
7.   Good written and oral English communication skills.  


职位 3：  ASIC Design Engineer / 数字设计工程师  


工作职责：  
1.Design and implement digital circuits in advanced CMOS technology;  
2.Develop and improve new and existing circuit solutions;  
3.Present and receive technical feedback at reviews;  
4.Document RTL design and communicate with other designer;  
5.Understand system level architectural design;  
6.Work with team members to resolve technical issues;  


职位要求：  
1.Bachelor, Master or above in Electronic, Communications, Microelectronics Engineering, Computer Science or relative major;  
2.At least 3+ years of experience in digital design based on high-level languages (preferable Verilog), with knowledge of ASIC FE design flow, including coding, simulation, verification, synthesis, DFT and STA;  
3.Familiar with front end EDA tools;  
4.Familiar with FPGA prototyping development;  
5.Good written and oral English communication skills.  


职位 4：  Sr. Verification Engineer/高级数字验证工程师  


工作职责：   
1.   Create, developing and maintain verification testbench environment;   
2.   Developing test case and regression plans;  
3.   Work close with designers and understanding the expected functionality of designs;  
4.   Running RTL and gate-level simulations/regression;  
5.   Code/functional coverage development, analysis and closure;  
6.   Release the documents during the verification flow. Such as verification plan, usage of the verification environment, simulation result of test cases, verification coverage report, etc.  


职位要求：   
1.   Minimum of 5 years design/verification experience (test plan, test bench, assertions,? debugging designs, code coverage etc.);  
2.   Knowledge in ASIC/FPGA design process and verification tools/env (UVM/OVM…);  
3.   Familiar with design and verification languages (Verilog, System Verilog, SVA etc.);  
4.   Familiar with C/C++, Perl/Python and other script/automation skills (tcl, makefile etc);  
5.   Additional qualifications include: Good IC verification skills and basic knowledge of logic or circuit design, good communication and problem solving skills, English and other foreign languages;  


职位 5：  Verification Engineer/数字验证工程师  


工作职责：   
1.   Understanding the expected functionality of designs;  
2.   Designing and developing verification environment;   
3.   Running RTL and gate-level simulations/regression;  
4.   Code/functional coverage development, analysis and closure;  
5.   Release the documents during the verification flow. Such as verification plan, simulation result of test cases, verification coverage report, etc.  


职位要求：   
1.   Minimum of 3 years design/verification experience (test plan, test bench, assertions,? debugging designs, code coverage etc.);  
2.   Familiar with design and verification languages (Verilog, System Verilog, SVA etc.);  
3.   Scripting and automation skills (tcl, perl, makefile etc) a plus;  
4.   Additional qualifications include: Good IC verification skills and basic knowledge of logic or circuit design, good communication and problem solving skills, English and other foreign languages;  




有意者随时联系我，微信 18795875089，或发简历到 anna.gao@hibohr.com ，欢迎帮忙扩散~~~     
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