华芯通招聘处理器设计/验证/modeling攻城狮

processor

华芯通半导体是由贵州省政府和qualcomm公司共同出资成立的集成电路设计公司，产品是高性能的ARM服务器芯片，目前处理器设计团队扩招，职位open，欢迎大家的加入！

华芯通处理器设计团队的优势：
1）基于qualcomm业内领先的falkor处理器
2）工作环境好，团队气氛融洽
3）团队经验丰富，身处其中能够获得快速的成长
4）能够接触业内顶尖的qualcomm/ARM专家
5）待遇从优，弹性工作时间，带薪年假，团队建设，该有的都有

欢迎大家加入我们！
简历请投递至：yongbin.yao@hxt-semitech.com
                    tjuyaoyongbin@163.com (公司邮箱接收外网邮件有限制，请同时发送到这个邮箱)


招聘的职位有处理器设计/验证/modeling，具体的职位要求如下：

Job Title: CPU Micro-architect and Design engineer

Location: Beijing/Shanghai

Position Description

Develop the next generation of Huaxintong'sindustry-leading custom ARM-compatible CPUs. Involved in all phases of productdevelopment, from proving-out initial high-level concepts down to modeling thebits of individual registers.

Responsibilities

1.
Design andimplement CPU microarchitecture.

2.
Work with CPUperformance modeling team and verification team to design the major blocks ofthe Huaxintong's next generation custom CPU.

3.
Use HardwareDescription Language to design models of the Instruction Unit, Execution Unit,Storage Unit, Caches and coherence bus system.

4.
Employsynthesis, STA and power tools to achieve improve performance with reasonableoverhead.

Qualifications

Minimum:

1.
Master degreeor above

2.
Industryexperience in a high-performance IC design.

Preferred:

3.
Experience with CPUfunction unit, such as instruction unit, execution unit and O3 related logic.

4.
Experiencewith CPU memory system unit, such as Load/Storage unit, TLB, MMU.

5.
Experiencewith coherence protocol implementation, such as ACE, CHI/CHIE.

Skills and Knowledge

1.
Verilog/VHDL

2.
Knowledgeabout RISC and CPU architecture

3.
Knowledgeabout high performance logic design techniques

4.
Knowledge ofverification and good communication skill with verification team

5.
The skill touse simulation/synthesis/lint/CDC tools

Job Title: CPU Performance Modeling Engineer

Location: Beijing/Shanghai

Position Description

Develop the next generation of Huaxintong'sindustry-leading custom ARM-compatible CPUs. Involved in all phases of productdevelopment, from proving-out initial high-level concepts down to modeling thebits of individual registers.

Responsibilities

1.
Predict CPUand SOC performance before the silicon is available.

2.
Work with CPUmicro architects to define the major blocks of the Huaxintong's next generationcustom CPU.

3.
Use C++ todevelop models of the Instruction Unit, Execution Unit, Storage Unit, Cachesand coherent bus.

4.
Employ the C++model to perform pre-silicon performance studies/predictions of the CPU usingindustry standard benchmarks.

5.
Analyze theresults of the performance studies and recommend microarchitecture changes toimprove the results.

Qualifications

Minimum:

1.
Master degreeor above

2.
Industryexperience in CPU performance modeling

Preferred:

1.
Experience inmicroarchitecture implementation.

2.
Familiaritywith on/off chip coherence design or Implementation, such as ACE, CHI/CHIE,CCIX.

3.
Familiaritywith Linux software development

4.
Familiaritywith industry standard benchmarks

Skills and Knowledge

1.
C++programming

2.
Verilog/VHDL

3.
Knowledgeabout RISC and CPU architecture/micro architecture

4.
Knowledgeabout high performance logic design techniques