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junior + senior+staff 都在招聘。有意向可以联系 CHINAXDWL@163.com
site:上海
谢谢～
Job Description
-Participate in high speed SERDES PHY design, such as PCIE, USB and SATA.
-Will be involved in the whole ASIC design flow from RTL coding through P&R support, which includes logic design, DFT planning and implementation, logic synthesis, power optimization, static timing analysis and sign-off.
-Will also work closely with analog design teams on IP integration, with P&R engineers on chip floor planning and timing optimization, and with product/test engineers on ATE tests. Work closely with frontend and backend design teams, as well as test engineers.
Job Requirement
-BS or MS in EE/CS
-Excellent knowledge of RTL design and verification.
-Hands-on experience with Verilog, C/C++, Perl, Tcl.
-Experience in PCIE,USB and SATA is a plus. |
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eetop公众号
创芯大讲堂
创芯人才网
发表于 2017-11-15 13:46:23
楼主
JD 是从 51 上 copy 的 ， 招验证的。