【Synopsys武汉】招数字设计工程师Digital Design engineer(Timing, DFT Validation)

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ASIC Digital Design engineer(Timing, DFT Validation)

Location: Wuhan

Email: qyzhong@synopsys.com

As a member of the Synopsysmixed signal IP team you will work with global teams to define and developtiming constrain validation platform.  

PositionResponsibilities:

·
Drive andwork closely with RTL, implementation and methodology teams to establish a flowthat brings the RTL and STA constraints into the in-house infrastructure forSTA analysis

·
Use theregression infrastructure to provide feedback to the RTL team on thetiming-cleanliness of the design and the quality of the STA constraintsthemselves

·
Participatein the discussions/reviews of the regression results to improve the correct andefficiency of the flow

Requirements:

Must have BSEE in EE with 5+years of relevant experience or MSEE with 3+ years of relevant experience inthe following areas:

·
Demonstratesgood communication skills in English

·
Goodskills in scripting and automation

·
Experienceswith timing/Synthesis constraints and floorplan-aware synthesis

·
Knowledgeof Verilog and IC design development cycle

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希望大家多多投递：Xuan.qin@synopsys.com,Synopsys

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