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1. Have the high work enthusiasm;
2. Have strong sense of time;
3. Have the ability to work independently;
4. Have the high communication ability;
5. Familiar with System-Verilog, including the class/constraintrandom/assertion/coverage information;
6. Familiar with UVM;
7. Familiar with VCS or /Verdi tools;
8. Familiar with C Language, Linux c-shell script;
9. Preferred to be familiar with DisplayPort protocol,including MST/SST/HDCP 2.2/DSC 1.2; 10. Desired to have the ability to developthe Verification Plan; 11. Have the ability to create test cases;
12. Have the ability to trace the simulation bugs;
13. Preferred to have the ability to supply the code & function coveragereport & database;
咨询及简历投递邮箱:juanjuan.wei@altran.com bingyue827828@163.com
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