Cadence 上海/ 北京招聘大量前端设计工程师 / 后端设计工程师---2017.9月最新职位

springyang

Cadence 上海/ 北京招聘大量前端设计工程师 / 后端设计工程师， 有意者请将简历发至541515639@qq.com， 邮件标题中请注明应聘职位，谢谢！

Senior/ Principal Front-end DesignEngineer

Location: SH/BJ

           Position Description:

Ø
Deliver/implement DDR/HBM IP. The engineershould be able to act as a strong team member and contributor. Exercisejudgment within generally defined practices and policies.

           Specific duties include:

Ø
Proficiency in logic design, simulation

Ø
Proficiency in Verilog and its simulationenvironment

Ø
Good knowledge of IC design

Ø
At least seven year experience working ondigital IC development projects, excellent communication skills and the uncannyability to both lead and contribute in a cooperative team environment.

            Position Requirements:

Ø
Essential Qualifications: Must have BS degreewith 9~12+ years of applicable experience, MS degree with 7~10+ years ofapplicable experience in electrical engineering, microelectronics, comparableengineering science or solid state physics.

Ø
Essential that the individual demonstratesstrong communication, verbal and written.

Requires good communication skills in English.

Ø
Will have demonstrated successful completion of10+ design projects as an individual contributor

Ø
Familiar with JEDEC-DDR/HBM, DFI and AMBAprotocols and have DDR project design experience

Title: Principal/Lead Physical Design Engineer

Location: Shanghai

           Position Description:

Ø
Perform physical design implementation,including floor planning, power grid design, place and route, clock treesynthesis, timing closure, power/signal integrity signoff, physicalverification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.

Ø
The candidate will have the opportunity to workon many varieties of challenging designs, i.e. low power and high speed design.The responsibility includes participating in or leading next generation PHY IPphysical design, methodology and flow development.

           PositionRequirements:        

Ø
BSdegree with 5~10+ years of applicable experience, MS degree with 4~8+ years ofapplicable experience in electrical engineering, microelectronics. Experiencedwith ASIC design flow, hierarchical physical design strategies, andmethodologies and understand deep sub-micron technology issues. Solid knowledgeon LP Design, static timing analysis, EM/IR-Drop/crosstalk analysis, physicalverification, DFM. Successful track records of taping out complex,16nm/10nm/7nm chips. Automation and programming-minded, solid coding experiencein Makefile/Tcl/Tk/Perl. Self-motivated, able to work independently or as ateam player, excellent verbal and written communication skills in English.

springyang

update