The following are not supported:
• SPICE-top design
The top-level design hierarchy must be described in Verilog.
• Doughnut configuration design
Transistor-level blocks can instantiate some transistor-level
subcircuit and Verilog-A models, but not Verilog modules.
• Real-type ports in Verilog
• Cross-module references (XMR) over the Verilog and
transistor-level boundary
• $fsdbdumpvars system task
/2 
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发表于 2012-7-30 11:43:46