哪位仁兄会使用Nanosim与VCS进行数模混合仿真啊？

goose99 · 发表于 2012-7-30 11:43:46

XIEXIE

dandan58 · 发表于 2012-8-23 12:04:43

谢谢2楼提供的资料，学习了

albert_eetop · 发表于 2012-8-24 15:20:06

The following are not supported:
• SPICE-top design
The top-level design hierarchy must be described in Verilog.
• Doughnut configuration design
Transistor-level blocks can instantiate some transistor-level
subcircuit and Verilog-A models, but not Verilog modules.
• Real-type ports in Verilog
• Cross-module references (XMR) over the Verilog and
transistor-level boundary
• $fsdbdumpvars system task

能不能支持hspice和vcs的联合仿真啊？