Cadence 上海/北京招聘数字前端设计/验证工程师--2017.8最新职位

springyang

Cadence 上海/北京招聘数字前端设计/验证工程师，如有兴趣请速将简历发至541515639@qq.com, 邮件标题中请注明应聘职位，谢谢！
职位描述：

1. Title: Principal/LeadVerification Engineer (数字前端验证)

Location：SH/BJ

    Position Description:

Deliver/implementadvanced verification solutions by utilizing Cadence’s Incisive Verificationproduct portfolio. The engineer should be able to act as a strong team memberand contributor, leading team projects and initiatives. Exercise judgmentwithin generally defined practices and policies.

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Specific duties include:

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Deep understanding on ASIC design and verification flow

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Excellent knowledge of advanced verification methodologylike eRM/OVM/UVM/VMM

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Familiar with Cadence’s Incisive Plan to ClosureMethodology (IPCM)

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Proficiency in System Verilog, System C and/or e (Specman)

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Developing and using Verification Components (eVC,OVC,UVC,VIP)

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Developing and using assertion based verification andformal analysis methods

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Skilled in scripting language, such as Perl,Cshell,Python,Makefile

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Assessing the project verification requirements

    Position Requirements:

     Essential Qualifications:

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BS degree with 7+ years of applicable experience, MS degreewith 4+ years of applicable experience in electrical engineering,microelectronics, comparable engineering science or solid state physics.  

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Essential that the individual demonstrates strongcommunication, verbal and written. Requires good communication skills inEnglish.

    Desirable Qualifications:

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Will have demonstrated hands-on experience and expertisewith Cadence verification design tools or equivalent tools, flows and methodologiesrequired to execute a verification project.

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Will have demonstrated successful completion of 3+verification projects as an individual contributor

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Will have DDR project verification experience

2. Principal Front-endDesign Engineer

Location：SH/BJ

     Position Description:

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Deliver/implement DDR/HBM IP. The engineer should be ableto act as a strong team member and contributor. Exercise judgment withingenerally defined practices and policies.

   

     Specific duties include:

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Proficiency in logic design, simulation

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Proficiency in Verilog and its simulation environment

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Good knowledge of IC design

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At least seven year experience working on digital ICdevelopment projects, excellent communication skills and the uncanny ability toboth lead and contribute in a cooperative team environment.

  

     Position Requirements:

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Essential Qualifications: Must have BS degree with 9+ yearsof applicable experience, MS degree with 7+ years of applicable experience inelectrical engineering, microelectronics, comparable engineering science orsolid state physics.

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Essential that the individual demonstrates strongcommunication, verbal and written.

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Requires good communication skills in English.

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Will have demonstrated successful completion of 10+ designprojects as an individual contributor

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Familiar with JEDEC-DDR/HBM, DFI and AMBA protocols andhave DDR project design experience

3. Sr. Principal Front-endDesign Engineer  

(Location: SH/BJ)

     Position Description:

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Deliver/implement DDR/HBM IP. The engineer should be ableto act as a strong team member and contributor. Exercise judgment withingenerally defined practices and policies.

   

     Specific duties include:

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Proficiency in logic design, simulation, synthesis, STA andtesting

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Proficiency in Verilog and its simulation environment

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Good knowledge of IC design

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At least ten year experience working on digital ICdevelopment projects, excellent communication skills and the uncanny ability toboth lead and contribute in a cooperative team environment.

  

     Position Requirements:

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Essential Qualifications: Must have BS degree with 12+years of applicable experience, MS degree with 10+ years of applicableexperience in electrical engineering, microelectronics, comparable engineeringscience or solid state physics.

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Essential that the individual demonstrates strongcommunication, verbal and written.

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Requires good communication skills in English.

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Will have demonstrated successful completion of 15+ designprojects as an individual contributor

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Familiar with JEDEC-DDR/HBM, DFI and AMBA protocols andhave DDR project design experience

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