【招聘】Availink中天联科诚招ASIC Logic Design Engineer--北京

Availink-Job

ASIC Logic Design Engineer

Location:  Beijing, China

Responsibilities:
* In this role you will participate in design and implementing RTL for highly complex FHD/UHD multimedia SOC.
* Responsibilities include micro-architecture definition, logic design, DFT and timing closure; other responsibilities may include block level verification, FPGA prototyping and chip testing.

Qualifications:
* MS degree in Electrical Engineering or Computer Science
* 1~4 years experience in micro-architecture and RTL logic design and verification (Verilog and/or VHDL)
* Knowledge in audio/video multimedia embedded SoC
* Good knowledge in RTL design flow: Simulation, Synthesis, Static Timing Analysis, Formal etc.
* Good lab skills. Working knowledge of FPGA based prototyping
* Shell and C programming skills
* Excellent communication and presentation skills
* Well organized, methodical, and detail oriented
* Team player, and easy to work with

Availink-Job

有意向的小伙伴儿们，请联系我哦：peng.song@availink.com
等着简历来砸我！！！