上海张江创业公司-协议软件，RFIC, 数字前端，数字验证，基带算法岗位

hamy

如题，有兴趣可以发简历到hamy@hibohr.com，或者加微信 13512136297

软件工程师leader

(1) 通信/电子工程/计算机 硕士以上学位，无线通信终协议栈软件开发工作经验三年（含）以上；

(2) 有至少一项如下无线通信制式协议栈软件开发的工作经验： WiFi/BLE, LTE (LTE 尤佳);

(3) 熟悉SOC基础软件模块，如芯片Boot,  SPI, UART等常用接口的驱动；

(4) 熟悉SOC芯片内部Firmware的开发、调试和验证；

(5) 优秀的C编程和阅读，嵌入式软件开发，调试技巧和能力；

(6) 良好的人际交往和跨地区团队技术沟通和协调能力；

(7) 良好的英语听，说，写能力；

RF IC Designer

职位介绍：

1. 设计各种无线通讯芯片的射频电路模块，包括但不限于以下模块：LNA，Mixer，PA，Filter, PLL

2. 独立完成或协助版图工程师完成高质量的版图设计

3. 协助应用工程师完成相关模块的测试任务

任职要求：

1. 本科硕士阶段成绩优秀

2. 扎实的模拟射频电路设计基础

3. 设计过无线收发机中射频模拟电路，有相关流片经验

Digital Design Engineer

Job Responsibilities:

[size=10.0000pt]1. Block-level architecture definition and design

[size=10.0000pt]2. Writing design spec and report

[size=10.0000pt]3. Block-level RTL implementation

[size=10.0000pt]4. SOC integration

[size=10.0000pt]5. Simulation/Verification at both block level and system level

[size=10.0000pt]6. Block-level synthesis and timing analysis

[size=10.0000pt]7. FPGA/silicon validation on related modules

[size=10.0000pt]8. Spec & micro architecture definition based on C/C++/SystemCalgorithm model.

Job Requirements:

[size=10.0000pt]1. BSEE or MSEE with 2-5year experience of digital design.

[size=10.0000pt]2. Solid knowledge of digital design building blocks (Data-path, Filters, FIFO...)

[size=10.0000pt]3. Strong skills of Verilog RTL coding, verification and debug.

[size=10.0000pt]4. SOC/FPGA design/validation experience

[size=10.0000pt]5. DFT experience is a plus

[size=10.0000pt]6. Familiar with System-verilog language is a plus.

[size=10.0000pt]7. Good communication skill, team work spirit, self-motivated.

DigitalVerification Engineer

Job Responsibilities:

[size=10.0000pt]1. Define verification plan regarding functional design specification

[size=10.0000pt]2. Develop various verification model

[size=10.0000pt]3. Perform co-verification of processor models and RTL including application software and firmware verification

[size=10.0000pt]4. Support the development of multi abstraction/views to enable a thorough Soc verification from unit level to system level

[size=10.0000pt]5. FPGA validation and chip testing

Job Requirements:

[size=10.0000pt]1. BSEE or MSEE degree with 2~5 years experience in ASIC/complex SoC verification. Some RTL design/modeling experience is a plus.

[size=10.0000pt]2. Proficient with  UVM

[size=10.0000pt]3. Proficient with system Verilog and various shell language(perl, csh, tcl, sh, etc)

[size=10.0000pt]4. FPGA validation and chip validation experience  is a plus.

[size=10.0000pt]5. Proficient with AMBA AHB/AXI/APB protocol and have knowledge of various peripheral protocol which like I2C, UART, USB etc

[size=10.0000pt]6. Experience of SOC designs with embedded processor cores and their integration with other system components including memory subsystems and peripherals.

[size=10.0000pt]7. Familiar with Microprocessor and/or DSP instruction sets and how low level driver software integrates into SOC architecture.

[size=10.0000pt]8. Familiar with HDL languages, simulation tools and testbench design, low level assembler languages and C, or C++, scripting languages

基带算法工程师

职位描述:
1. 无线通信物理层基带算法研究和开发，包括信号同步与检测，调制与解调，编解码等；
2. C和Matlab算法建模；
3. DSP上调试优化算法性能;
职位要求：
1. 通信原理、信号处理、电子工程专业毕业，硕士及以上学历；
2. 熟悉调制解调算法，软件发射机和接收机原理；
3. 熟悉FPGA设计，嵌入式算法实现，有参与芯片设计的背景知识或经验；
4. 熟练掌握MATLAB/C仿真工具软件进行算法仿真和设计验证；
5. 具备良好团队合作精神，能够承受硅谷风格初创企业的工作压力；
6. 优先考虑： 工作3年以上，有5G、4G、3G、LTE、Bluetooth、Zigbee、WiFi等协议标准研究工作经历者优先考虑。

sailorchu

什么公司能透露下么？

mrfish616

什么待遇能透露下么？

hamy

创业型公司，薪水暂无明确范围。一般来说薪水会在30-50万左右

rickbest

回复 4# hamy

税前还是税后？

hamy

回复 5# rickbest


   税前