Design Compiler has many exciting new features and changes for the M-2016.12 release. This update training session explores these enhancements and more. This training is delivered in MP4 video format.
Introduction (3:12)
- Enhanced Productivity Highlights
- 15% faster runtime compared to L-2016.03
- 30% runtime reduction using optimize_netlist -area compared to L-2016.03
- Faster multicorner-multimode synthesis compared to L-2016.03
- Multicore synthesis on 8 cores with 1 license
Module 1: Optimization I (7:04)
- Support for Path Groups in Pipelined-Logic Retiming
- Faster Multicorner-Multimode Runtime
- Unconnected Logic Propagation Across Hierarchy with Boundary Optimization Disabled
- Improved Congestion Optimization Using compile_prefer_mux
Module 2: Optimization II (7:19)
- Placement-Aware Banking of Bused Registers
- Timing-Aware Multibit Debanking
Module 3: Correlation to Layout (6:21)
- Cell and Pin Density Maps
- Support for Up to 31 Routing Layers
- Clustering Logic Modules to Minimize QoR Variations
- Layer Promotion Constraints for IC Compiler II
Module 4: Improved Usability (9:50)
- Reading and Writing Compressed Environment Files
- Accurate Memory Number for Multicore
- Multiplier Architecture Reporting
- Improved Multiplier Architecture Control
- Writing Multibit Components Into a File
- Controlling Automatic Path Group Creation
Module 5: Improved Language Support (3:46)
- SystemVerilog Parameters Without Default Value
- Elaboration System Tasks Support
Module 6: Support for RM+ Flows (6:40)
- Support for RM+ Flows In Design Compiler Reference Methodology L-2016.03-SP4
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发表于 2017-2-20 09:46:24
