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华芯通是一家取得高通授权,开发基于ARM的大规模服务器芯片,现在上海地区高薪大量招聘芯片验证工程师。
SOC level的验证非常有趣,可以拓宽你的视野,增加系统级的knowledge,包括多最新ARM多核架构,系统级的boot流程,多种多样的高速外设,
对自己的技术能力和职业生涯规划将会帮助很大。
上海办公地点: 展想广场1号楼(距离2号线广兰路地铁站300米左右)
职位title: senior/staff/senior staff engineer
只要你有兴趣,随时发送简历到qiang.wang@hxt-semitech.com
Job Description: Responsibility:
Responsible for all aspects of verification on next generation integrated processors, including developing testbenches, modeling, assertions/checkers/monitors, test plan & test development, regressions, and infrastructure development. Responsibility includes participating in the pre-silicon blocks, chip, multi-chip and system level verification strategy:
- Verification of SoC level design using random methodologies – Test Planning, Implementation and Execution.
- Develop System Verilog (UVM) random sequences and methods.
- Maintain and Interface with existing random generators, models and APIs
- Integration of random modules to various testbenches.
- Executing verification through directed and random tests for its functionality and interface protocols and tracking bug reports. Creation of the needed test libraries, test API, simulation models. Debugging regression failures and identify the cause.
- Strong documentation and communication skills.
- Ability to work well in a dynamic, fast-paced, pressure filled, across multiple sites North America and Asia
- Flexible in terms of responsibilities and hours.
Requirement:
- Complex ASIC/SOC Design Verification, direct experience in SOC or Processor is preferred.
- Good knowledge of SystemVerilog and UVM is a plus.
- Good knowledge of Verilog/C/C++/System C/SystemVerilog.
- Verification insights into random techniques.
- Verification of large scale ASICs.
- Experience in power verification is an asset.
- Verification of Virtualization Components is an asset.
- C and C++ software development and scripting languages (Perl, C Shell, Makefile, …) experience.
- Background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA). |
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