华芯通 sr/staff ASIC verification engineer 招聘

ultrasparc1

Job Title: Staff IP Design Verification Engineer
Location: Beijing/Shanghai
Position Description
Lead or co-lead the IP verification team to finish one IP or subsystem verification, take charge of the verification quality and the schedule
Responsibilities
Lead the IP verification, and decompose the tasks into each team member
Create the testplan and review with team members and designers; make sure the testplan is completed, detailed, and measureable.
Create the random constraint testbench per requirements; make sure team members could implement correctly.
Create the random/direct testcases to cover IP design features, and make sure all required featured was covered.
Debug the testbench and RTL, and report the bug to designer; follow up the whole IP verification status
Finish the verification tasks in time

Qualifications
Education and Experience
Bachelor or above with 3~9 years of work experience

Skills and Knowledge
Verilog/System Verilog
UVM
Perl/Python
DDR controller and DDR PHY related work is a big plus.
C++ is an additional plus
Formal verification experience is an additional plus
PCIE/SATA/USB/Ethernet/SPI/I2C/etc. experience is an additional plus
ARM related experience is an additional plus

please send resume to zheng.shang@hxt-semitech.com if you are interested.