IC Compiler II M-2016.12 Incremental Training

ViaEDA · 发表于 2017-2-3 15:27:02

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本帖最后由 ViaEDA 于 2017-2-7 16:06 编辑

IC Compiler II M-2016.12 Incremental Training is delivered in thefollowing four main parts:

Library Preparation

The library preparation training consists of the following modules:

Library Preparation Part I
- Loading logic lbraries
  - read_lib Installation Enhancement
  - Frequency-Dependent Maximum Capacitance and Maximum Transition
  - Selective PVT Loading
  - Scaling Support for On-Chip Variation and Cell Electromigration
- Using Block Labels in the ETM Flow
- Loading LEF Files
  - Controlling How read_lef Derives the Cell Boundary
Library Preparation Part II
- Generating Frame Views
  - Error Handling for Invalid Frame Generation Options
  - Creating Frame Views for Subblocks of a Hierarchical Block
  - Specifying the Top Layer for Core Blockages
  - Removing Non-Pin Shapes to Reduce Obstacles
  - Creating Zero-Spacing Blockages Around Pins
  - Creating Zero-Spacing Blockages Around Non-Pin Shapes
  - Color-Based Frame Generation Flow
- Library Reporting Enhancements
- Using Block Labels When Writing LEF Files

Hierarchical Implementation Flow

The following figure highlights the new features in the hierarchicalimplementation and GUI flow:

The hierarchicalimplementation flow training consists of the following modules, which includeadditional new features:

Design Planning Enhancements:
- Check and Analyze for Design Planning
- Off-edge Macro Placement
- PG Enhancements
- Pin Placement for Specified Nets
- Budgeting With Annotated Delay
Clock Trunk Planning:
- Overview
- How to Use
- How to Check
Graphical User Interface Enhancements
- GUI Infrastructure
- Layout Editing
- Layout Analysis
- Relative Macro Placement
- Hierarchy Browser
- Clock Tree Synthesis
- ECO
- HTML Man Pages
Top Level
omotion o Clock-Related Data
- Integration of Hierarchical Design Checks Into Mega Commands
- Power Abstracts and Power Report for Designs With Physical Hierarchy
- Support for Global-Route-Based High-Fanout Synthesis and DRC Violation Fixing
- Signal Electromigration (EM) Analysis For Hierarchical Designs
- Nondefault Routing Rule (NDR) Handling When Creating and Merging Abstracts

Flat Implementation Flow

The following figure highlights few of the new optimization features inthe flat implementation flow:

The flat implementation flow training consists of the following modules,which include additional new features:

Placement and Optimization
Clock Tree Synthesis
Multisource Clock Tree Synthesis
Routing
IC Validator In-Design

Common Features

This training covers new features for the data model,timing, electromigration, chip finishing, multivoltage, engineeringchange orders (ECO), and design analysis.

The training consists of the following modules, which include additionalnew features: