AMD最新招聘上海北京 CPU/GPU/Video/ISP设计验证、DFT、版图、软件、硬件

HR_IC_Talent

AMD社会招聘

上海/北京超100个职位，总有一个适合您！

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AMD社招职位多多，欢迎优秀的工程师，发简历到 icer365@163.com，
第一时间回复您最想了解的问题。

主要招聘职位（详见下文列表）：数字IC设计、数字IC验证、DFT工程师、物理设计、数字版图设计、前端集成、ISP/Camera、Video IP算法架构、GPU架构、SoC验证、显卡驱动、BIOS、软件、项目经理、硅仿真Lead等领域。

AMD股票（AMD工作机会和前景）：从2015年8月份的最低点1.61美元/股，到2016年12月的最高点12.34美元/股，说明公司近两年的发展进入了稳定的上升期，AMD的技术和产品得到了市场和资金的认可。GPU、APU和CPU的业务量都在增长，中国区的员工数量从1000人增长到1500人，未来一年AMD的GPU/CPU/APU/VR/AR/等业务继续快速增长，继续各类工程师。欢迎各位硬件、软件、集成电路设计验证、后端实现、DFT工程、FPGA开发工程师、视频、3D等领域的各领域的优秀工程师加入。

AMD的优势：

A. 相比其他外资企业，AMD是少数将核心研发中心放在中国，中国员工可以查看GPU等核心IP的文档和代码；有利于员工的长期职业发展

B. 相比国内强制的打卡和工作时间考前，AMD的工作时间弹性化，网络VPN便于员工最大化的提高工作效率，有利于员工的生活和工作的平衡

C. 福利待遇也不错哦，补充公积金，10天以上的年假，股票

huatiantian

thanks for sharing!!!daiyurehe?

HR_IC_Talent

待遇不错啊。
很大一部分工程师都是10年左右的，他们历经了大大小小的外资、国企、私企和研究院所。长久的职业发展和工作生活的平衡可能是这个level的人比较看重的吧。社招的数量远远大于校招（基本不校招）。
当然如果想要很高的薪资，IC行业不是的好的选择。

renliang

必须顶起哦

HR_IC_Talent

回复 1# HR_IC_Talent

急招 数字设计验证工程师地点：上海 、北京
职位：Sr.(3年以上)， MTS (6年以上)， SMTS (10年以上)

Sr./MTS/SMTS ASIC Design Verification Engineer

Job Location: Beijing/Shanghai

Job description:

We are currently looking for engineer who will beresponsible for design verification of cutting edge GPU projects. Qualifiedcandidate will participate in and lead SoC level function verification domainsincluding:

1.            SoC DVtestbench and infrastructure development and maintenance

2.            Createand execute SoC testplan including data-path and interrupt, virtualization,security, power management, etc.

3.            Implementdirected and random test cases in C++/SV, as well as checkers and assertions

4.            Supportintegration and qualification of all the IPs for SoC

5.            Help toimprove DV environment building flow

Requirement:

-   MS with 7+ or BSwith 9+ years’ experience in ASIC/SoC design verification

-   DV lead experienceis a must

-   Hand-on experiencein all domains of complex ASIC DV flow from plan to coverage, both

-   Knowledgeable inC++ & SV development, familiar with scripting languages likeRuby/Perl/Makefile…

-   Strong problemsolving and communication skills

-   Knowledge oncomputer architecture and PCIe devices is highly preferred

-   Good knowledge onverification methodologies like UVM is a big plus

-   Experience inpower-aware verification is an asset

HR_IC_Talent

回复 4# renliang


   急招 数字设计验证工程师地点：上海 、北京
职位：Sr.(3年以上)， MTS (6年以上)， SMTS (10年以上)

Sr./MTS/SMTS ASIC Design Verification Engineer

Job Location: Beijing/Shanghai

Job description:

We are currently looking for engineer who will be responsible for design verification of cutting edge GPU projects. Qualified candidate will participate in and lead SoC level function verification domains including:

1.            SoC DV testbench and infrastructure development and maintenance

2.            Create and execute SoC testplan including data-path and interrupt, virtualization, security, power management, etc.

3.            Implement directed and random test cases in C++/SV, as well as checkers and assertions

4.            Support integration and qualification of all the IPs for SoC

5.            Help to improve DV environment building flow

Requirement:

-   MS with 7+ or BS with 9+ years’ experience in ASIC/SoC design verification

-   DV lead experience is a must

-   Hand-on experience in all domains of complex ASIC DV flow from plan to coverage, both

-   Knowledgeable in C++ & SV development, familiar with scripting languages like Ruby/Perl/Makefile…

-   Strong problem solving and communication skills

-   Knowledge on computer architecture and PCIe devices is highly preferred

-   Good knowledge on verification methodologies like UVM is a big plus

-   Experience in power-aware verification is an asset

HR_IC_Talent

UPDATE

yangzai1236

回复 1# HR_IC_Talent


   zhichi

semizhj

继续顶起看看

HR_IC_Talent

急招：数字验证工程师
地点：上海、北京

Sr./MTS/SMTS ASIC Design Verification Engineer
Job Location: Beijing/Shanghai

Job description:
We are currently looking for engineer who will be responsible for design verification of cutting edge GPU projects. Qualified candidate will participate in and lead SoC level function verification domains including:
1.        SoC DV testbench and infrastructure development and maintenance
2.        Create and execute SoC testplan including data-path and interrupt, virtualization, security, power management, etc.
3.        Implement directed and random test cases in C++/SV, as well as checkers and assertions
4.        Support integration and qualification of all the IPs for SoC
5.        Help to improve DV environment building flow

Requirement:
-   MS with 7+ or BS with 9+ years’ experience in ASIC/SoC design verification
-   DV lead experience is a must
-   Hand-on experience in all domains of complex ASIC DV flow from plan to coverage, both
-   Knowledgeable in C++ & SV development, familiar with scripting languages like Ruby/Perl/Makefile…
-   Strong problem solving and communication skills
-   Knowledge on computer architecture and PCIe devices is highly preferred
-   Good knowledge on verification methodologies like UVM is a big plus
-   Experience in power-aware verification is an asset