上海设计公司-前端 验证 DFT

hamy

张江某design service公司 因项目需求，需要大量数字前端 验证 DFT的人，有兴趣的可以发简历到hamy@hibohr.com，或者加微信13512136297 详细咨询


职位要求：

asic design engineer

1. Design top-of-the-line graphics processors, including specification, architecture, micro-architecture, implementation (using verilog), and verification;
2. Expected skills: 5+ years hands-on experience; Programming skills in Verilog;
3. Must be familiar with all stages of the ASIC design flow (including specification, architecture, and design implementation);
4. Highly motivated and skillful at solving difficult technical problems;
5. Knowledge of computer graphics and low-power design techniques a plus;
6. Experience of GPU shader design a plus.

SoC Logic Design Engineer

Responsibilities:
1. Play an important role in defining chip spec and devising chip architecture;
2. Develop challenging modules including module spec definition, macro architecture design, RTL coding, simulation and synthesis;
3. Carry out chip level verification or chip integration/implementation;
4. Help junior engineers to solve technical issues;
5. Support customers regarding chip applications.

Requirements:
1. Bachelor degree or above in EE, 3+ years experience;
2. Good knowledge of some of the following general IP: cpu/dsp, AMBA, DDR/SDRAM, Video( HEVC, MIPI…), parallel/serial peripheral module, DMA, interrupt, timer, GPIO ...
3. Good skill in the field of digital circuit design, whole digital design flow and EDA tools;
4. Key member in at least one successfully silicon proven challenging project;
5. Fluent in both English and Chinese;
6. Self motivated, good communication skill and team work spirit.

职位描述：
1. 负责定义芯片规格，并制定芯片架构；
2. 开发具有挑战性的模块，包括模块的规格定义，宏观架构设计，RTL编码，C编码，模拟和合成；
3. 开展芯片层面的验证, 整合/实现芯片模块；
4. 帮助初级工程师解决技术问题；
5. 指导客户正确应用芯片。

应聘要求：
1. 电子工程专业本科或以上学历, 3年以上的工作经验；
2. 熟悉部分下述IP：CPU/DSP，AMBA，DDR/SDRAM，Video, 并行/串行外围模块， DMA，中断；时序；GPIO 等；
3. 熟练运用数字电路设计，完整数字设计及EDA工具；
4. 至少曾在一个完整的成功流片的项目中担任过主要成员；
5. 中英文流利；
6. 勤奋踏实，良好的沟通能力和团队合作精神。

SoC Verification Engineer 验证工程师

Responsibilities:
1. Understanding the expected functionality of designs;
2. Developing testing and regression plans;
3. Designing and developing verification environment;
4. Running RTL and gate-level simulations/regression;
5. Code/functional coverage development, analysis and closure.

Requirements:
1. Minimum of 3 years design/verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.);
2. Knowledge in ASIC/FPGA design process and verification tools/env ( UVM/OVM…);
3. Familiar with design and verification languages (Verilog, System Verilog, SVA etc.);
4. Scripting and automation skills (tcl, perl, makefile etc) a plus;
5. Familiar with C/C++;
6. Knowledge of DDR/Video/arm/USB/PCIE , Low Power Verification with UPF and design experience is a plus;
7. Experience in CPU/DSP verification, including test plan and test bench development, test case development and test coverage assessment. and Knowledge of computer architecture and micro-architecture (pipeline, out-of-order, cache) is a plus
8. Additional qualifications include: Good IC verification skills and basic knowledge of logic or circuit design, good communication and problem solving skills;
9. Independent and self-managing.

Senior DFT

Responsibilities
1. Prepare the DFT plan for the SoC design;
2. SCAN/MBIST/BSD insertion for Flatten/Hierarchicaldesign;
3. Pre/Post simulation for test patterns;
4. Cooperate with timing engineer for test mode timing signoff;
5. Analog IP test implementation and simulation;
6. Support ATE engineer for chip testing debug, and analyze ATE log file to locate root cause of failure;
7. Communicate with customer about test related issue;
8. Formal check of pre-test and post test RTL/netlist.

Requirements
1. Bachelor's degree or above, majorin EE, CS or relevant;
2. Above 5years work experience to the one with Bachelor's degree and above 3years with Master's degree is required for Senior Engineer position;
3. Improve low test coverage to achieve higher coverage;
4. Skilledin csh/perl/tcl scripts;
5. Basic concept of timing analysis and P&R physical implementation;
6. Fluent in both English and Chinese;
7. Good team work spirit

职位描述:
1. 准备SoC芯片的测试计划；
2. 适用于扁平化/分层设计的SCAN/ MBIST/ BSD插入；
3. 测试向量的前/后仿真；
4. 配合时序工程师完成测试模式下的时序签收；
5. 模拟IP的测试实现和仿真；
6. 配合ATE工程师完成芯片测试调试, 根据ATE日志文件分析查找错误所在；
7. 与客户沟通交流测试相关事宜；
8. 前测试和后测试RTL/网表的一致性检查。

应聘要求:
1. 电子工程、计算机或相关专业本科或以上学历；
2. 本科学历申请高级工程师职位须具备5年以上相关工作经验, 硕士学历须具备3年以上相关工作经验；
3. 能够改进低测试覆盖率，实现高覆盖率；
4. csh/perl/tcl脚本编写技巧；
5. 时序分析以及P&R物理实现的基础知识；
6. 中英文流利；
7. 良好的团队合作精神。

hamy

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