成都芯片设计公司招聘-数字前端验证 DFT

hamy

公司地址：成都市天府软件园，并在北京中关村软件园、苏州工业园区以及美国设有分支研发机构。

高端集成电路设计是我们的主营业务。

公司基于目前国际主流的微处理器体系架构，设计符合中国市场实际需求的兼容型安全可靠服务器处理器芯片。

有兴趣可以发简历到hamy@hibohr.com，或者加微信13512136297
具体的职位JD

SOC 验证

职位描述/要求：

岗位职责：

1. 负责SoC系统级/模块级验证策略的定义

2. 负责SoC系统级/模块级UVM验证环境的搭建和验证工作

3. 负责SoC系统级/模块级测试向量的定义，开发，以及相应验证标准的制定

4. 参与SoC UVM验证架构的可行性和搭建的研究

5. 配合Design，FPGA或软件团队完成系统的验证工作

岗位要求：

1. 熟悉ASIC/SoC设计开发流程，熟悉SoC架构

2. 具有ASIC/SoC 验证经验，掌握模块级，系统级验证方法，包括前/后仿真

3. 熟悉IC设计相关的EDA工具的使用，比如NCSIM， VCS等

4. 熟悉Verilog, C, C++, 及验证语言 (SystemVerilog等)

5. 熟悉脚本语言，包括perl，shell， tcl等

6. 工作积极主动，有良好的分析问题，解决问题的能力

Job Responsibilities:

1. Responsible for design verification of cutting edge SoC projects.

2. Participate in all SoC level function verification jobs including: SoC DV testbench and infrastructure development and maintenance

3. Create and execute SoC testplan including data-path and interrupt, security, power management, etc.

4. Implement directed and random test cases in C++/SV, as well as checkers and assertions

5. Help to maintenance and improve DV environment building flow

Requirements:

1. MS with 5+ years experience in ASIC/SoC design verification

2. Hand-on experience in all domains of complex ASIC DV flow from plan to coverage

3. knowledgeable in Verilog, C, C++ & SV/UVM development, familiar with scripting languages like Perl/shell/tcl etc.

4. Strong problem solving and communication skills, DV lead experience is a big plus

5. Knowledge on computer architecture and high-speed IP interface protocol is preferred

6. Experience in power-aware verification is preferred

DFT 高级工程师

职位描述/要求：

岗位职责：

1. 负责DFT测试策略的制定和实现

2. 负责Module和SoC层次的DFT实现，包括Scan、Boundary Scan、MBIST以及IP test等

3. 负责Module和SoC层次的Synthesis，STA，时序收敛和等价性验证

4. 负责ATE测试中的向量产生和debug

5. 负责建立和维护DFT设计和验证自动化流程

6. 负责最终量产测试的向量产生和后硅验证

岗位要求：

1. 熟悉逻辑设计和验证流程

2. 精通Synthesis，STA，等价性验证

3. 对DFT设计（包括scan、mbist、jtag等）有实际项目的经验

4. 精通DFT设计工具（TestKompress, FastScan, Tetra max,等）

5. 能够熟练使用Perl、Tcl和Shell脚本编程

6. 具有使用逻辑仿真和debug工具的经验（vcs/ncsim/verdi等）

7. 具有分析，追踪和解决覆盖率损失、仿真错误、ATE测试失效等问题的能力

8. 具有ATE调试，测试向量调整等经验

Job Responsibilities：

1. Participate in SoC full Chip DFT architecture definition

2. Implement SoC DFT function including SCAN, Boundary SCAN, MBIST etc

3. Implement SoC synthesis, STA, logic equivalent check

4. Generate DFT related timing constraints and work for timing closure

5. Develop and verify high coverage and cost effective test patterns for the production test

6. Establish and maintenance the DFT flow

7. Pattern generation and debugging for ATE during mass product

Requirements:

1. MS with 5+ or Bachelor 8+ years experience in DFT design and verification, test pattern development

2. Good Knowledge of Scan/ATPG, MBIST and boundary scan and other DFT techniques

3. Good Knowledge of industry DFT tools like TestKompress, FastScan, Tetra max, etc

4. Good knowledge of digital SoC design, including STA, verification and equivalent check

5. Proficient in hardware description languages such as Verilog, System Verilog

6. Good Knowledge of script language, such as Perl, Tcl, Shell

后端工程师

职位描述/要求：

岗位职责：

1. 参与后端设计流程各阶段，完成模块和SoC后端设计

2. 负责完成整个芯片的netlist到GDII的产生，完成面积、时序和功耗等优化

3. 建立维护物理设计流程

岗位要求：

1. 熟练运用物理设计EDA工具，熟悉ICC/StarXRC/PT/Calibrate

2. 熟练掌握CTS/Timing closure/load check/fanout check/STA

3. 掌握低功耗、多电压域设计和实现

4. 熟悉perl/tcl/shell脚本语言

5. 有40nm及以下工艺流片经验

6. 有标准单元建库经验者优先

7. 有层次化IC设计经验者优先

Job Responsibilities:

1. Responsible for and own all aspects of physical design and physical verification effort at a block level.

2. Implement the full flow from netlist to GDS, optimizing the implementations for power, timing and area.

3. Develop, support and maintain physical design flows.

Requirements:

1. Good knowledge of EDA tools from Synopsys, Cadence and Mentor is required. In particular experience with ICC/StarXRC/PT/Calibrate is essential.

2. Good knowledge of VLSI process and device characteristics, to make optimal trade-off between performance and power.

3. Good knowledge of standard cell libraries, circuit design and layout.

4. Good understanding of static timing analysis (STA), EM/IR and sign-off flows.

5. Floor planning, place & route, power and clock distribution, pin placement and timing constraints generation.

6. Prior experience with 16nm, 28nm or finer geometries.

7. Good software and scripting skills (tcl, perl, shell)

8. Experience with hierarchical IC design is a plus

hamy

成都的，想回成都的可以看起来了