[AMD社招] Design Verification Engineer

RecruiterAMD

AMD 超威半导体上海研发中心招聘 Sr./MTS DV Engineer (SoC)；请有意向者将简历发送到 Cherry.Zhang@amd.com 谢谢
Job Location: Shanghai
JD Description:
-        Verification of SoC level design using random methodologies – Test Planning, Implementation and Execution.
-        Develop System Verilog (OVM) random sequences and methods.
-        Maintain and Interface with existing random generators, models and APIs
-        Integration of random modules to various testbenches.
-        Executing verification through directed and random tests for its functionality and interface protocols and tracking bug reports. Creation of the needed test libraries, test API, simulation models. Debugging regression failures and identify the cause.
-        Strong documentation and communication skills.
-        Ability to work well in a dynamic, fast-paced, pressure filled, across multiple sites North America and Asia
-        Flexible in terms of responsibilities and hours.