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本人也是一枚DesignVerification工程师,可以为您推荐。谢谢
如有兴趣请发简历到 ff_gate@126.com
有什么疑问也可发到这个邮箱
几个基本要求
一验证
1) Familiar with system Verilog and UVM methodology 2) Familiar with UNIX/Linux shell 3) Familiar with Perl script 4) Provide test plan basing on the design spec 5) Setup the module level and chip level DV environment
二FEINT1)Familiar and rich experience with SNPS EDAtools for RTL2GATE flow, i.e. DCT, Primetime, formality 2)Solid knowledge at FEINT technologies, i.e.synthesis, formality check, CDC, low-power design flow, and STA analysis
PS:以Contractor的形式工作在AMD |