【Nvidia】SENIOR DFT ENGINEER

NVHR

Responsibility:

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Planningat IP or fullchip level.

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Implementationand verification for MBIST/Scan/LBIST/ATPG.

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Design/verificationfor Clock/JTAG/Analog/DFT IP etc.

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Patterngeneration, release and ATE bringup.

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Responsiblefor DFT design/methodology/flow improvements.

Requirement:

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BSEErequired, MSEE preferred.

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3~10 years ofexperience in DFT/design field.

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Stronglogic Design and verification background with experience in STA.

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Mustpossess a strong knowledge of DFT including Scan, ATPG, Test Compression, JTAGand BIST.

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Capabilityto do DFT methodology work.

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Self-motivated andgood team player.

请将个人简历或者联系方式寄至carraz@nvidia.com信箱，我们将由专人与您联系。