/////////// ready 20k上升沿识别
always@(posedge i_clk)
begin
if (~i_rstn) begin
start<=0;
pos_ready<=0;
end
else begin
pos_ready <= ready;
start <= {(~pos_ready) & ready};
end
end
///////////Sclk 1M上升沿识别
always@(posedge i_clk)
begin
if (~i_rstn) begin
sent<=0;
pos_Sclk<=0;
end
else begin
pos_Sclk <= Sclk;
sent <= {(~pos_Sclk) & Sclk};
end
end
always @(posedge i_clk)begin
if (~i_rstn) begin
state <= 4'b0000;
o_TxD<=1;
end
else begin
case(state)
4'b0000: if(start)begin
state<=4'b0001;
// o_TxD <= RegData[0];
end
4'b0001: if(sent)begin
state<=4'b0010;
o_TxD <= RegData[0];
end
4'b0010: if(sent)begin
state<=4'b0011;
o_TxD <= RegData[1];
end
4'b0011: if(sent)begin
state<=4'b0100;
o_TxD <= RegData[2];
end
4'b0100: if(sent)begin
state<=4'b0101;
o_TxD <= RegData[3];
end
4'b0101: if(sent)begin
state<=4'b0110;
o_TxD <= RegData[4];
end
4'b0110: if(sent)begin
state<=4'b0111;
o_TxD <= RegData[5];
end
4'b0111: if(sent)begin
state<=4'b1000;
o_TxD <= RegData[6];
end
4'b1000: if(sent)begin
state<=4'b1001;
o_TxD <= RegData[7];
end
4'b1001: if(sent)begin
state<=4'b1010;
o_TxD <= RegData[8];
end
4'b1010: if(sent)begin
state<=4'b1011;
o_TxD <= RegData[9];
end
4'b1011: if(sent)begin
state<=4'b0000;
o_TxD <= RegData[10];
end