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Job Description: 1. Design for Test (DFT) RTL design and coding quality (CDC/LEDA) improvement. 2. Implement basic DFT schemes, including scan insertion, boundary scan, Mem BIST,DRC clean, ATPG and pattern simulation 3. Develop the high coverage and cost effective test patterns. 4. Support synthesis owner to fix DFT related netlist issues. 5. Support other teams for DFT related problems (such as ATE patterns debug) 6. Participate in SoC level DFT architecture definition. 7. Work with architect and designer to develop test plan Position Requirement: 1. Bachelor with 8+ year experience or Master with 6+ year experience. 2. Solid knowledge on DFT design, including JTAG, IEEE1500, MBIST and ATPG. 3. Basic knowledge of ASIC/SOC design flow, including coding, simulation, verification, synthesis and STA 4. Familiar with TetraMAX , DFT Compiler tool 5. Verilog coding experience. 6. Perl, TCL, Makefile coding experience 7. Good English communication skill and team work. 8. Fast learning and hard working. 请符合条件的工程师将简历发送至nina.zhang@amd.com,邮件主题标明来源,谢谢。 |