memory layout

jj_seu

Memory Layout Design Engineer 简历发 ic@hi-talent.com
Location: Shanghai Beijing
Responsibilities:
芯得客户 Memory Layout Design Engineer is working on cutting-edge Memory IP development for 芯得客户 worldwide customers, including memory compilers with high performance, e.g. SRAM, Register Array, Register File, etc. By employing the industry leading tools, state of the art methodology, and innovative semiconductor leading technologies ranging from 32nm to 14nm and beyond, you will be participating in the layout design, verification and extraction of memory compiler circuits.
Requirements:
1. College degree (or above) in EE or other related engineering field.
2. At least 3 years full-custom memory layout[img]file:///C:\Users\dell\AppData\Local\Temp\[LC3U)F{0XCAB)LKNIT0K@G.gif[/img]erification and RC extraction experience.
3. Experiences in memory layout design, including SRAM, DRAM, EEPROM, Flash, etc.
4. Familiar with physical verification tools (DRC,LVS,DFM,EMIR,etc).
5. Experiences in advanced technology node under 32nm/28nm and FINFET is preferable.
6. Good understanding of advanced semiconductor technology process and device physics.
7. Good English skills, communication skills, and willingness to work with a global team.
8. Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment.



Best Regards
Jane.Jin 金娟
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯得企业管理咨询有限公司
上海芯相会企业管理咨询有限公司
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