cadence ahdllib 中 veriloga mosfet level1 源代码

lansendiaoshen

下载了cadence 但是并没有找到ahdllib所以有没有人直接把这个mosfet level1 的veriloga 代码发上来...

ibubapa

thanks

Jeffrene

`include "discipline.h"
`include "constants.h"

// $Date: 1998/09/23 03:47:02 $
// $Revision: 1.2 $
//
//
// Based on the OVI Verilog-A Language Reference Manual, version 1.0 1996
//
//

`define n_type 1
`define p_type 0



//--------------------
// mos_level1
//
// -  A basic, level 1, Schichmann-Hodges style model of a MOSFET transistor
//
// vdrain:        drain  [V,A]
// vgate:        gate   [V,A]
// vsource:        source [V,A]
// vbody:        body   [V,A]
//
// INSTANCE parameters
//    width  = [m]
//    length = [m]
//    vto    = threshold voltage [V]
//    gamma  = bulk threshold []
//    phi    = bulk junction potential [V]
//    lambda = channel length modulation []
//    tox    = oxide thickness []
//    u0     = transconductance factor []
//    xj     = metallurgical junction depth []
//    is     = saturation current []
//    cj     = bulk junction capacitance [F]
//    vj     = bulk junction voltage [V]
//    mj     = bulk grading coefficient []
//    fc     = forward bias capacitance factor []
//    tau    = parasitic diode factor []
//    cgbo   = gate-bulk overlap capacitance [F]
//    cgso   = gate-source overlap capacitance [F]
//    cgdo   = gate-drain overlap capacitance [F]
//    dev_type   = the type of mosfet used []
//

module mos_level1(vdrain, vgate, vsource, vbody);
inout vdrain, vgate, vsource, vbody;
electrical vdrain, vgate, vsource, vbody;
parameter real width = 1u from (0:inf);
parameter real length = 1u from (0:inf);
parameter real vto = 1 from (0:inf);
parameter real gamma = 0 from [0:inf);
parameter real phi = 0.6 from (0:inf);
parameter real lambda = 0.05 from [0:inf);
parameter real tox = 1e-7 from (0:inf);
parameter real u0 = 600 from (0:inf);
parameter real xj = 0 from [0:inf);
parameter real is = 1e-14 from (0:inf);
parameter real cj=0 from [0:inf);
parameter real vj=0.75 exclude 0;
parameter real mj=0.5 from [0:1);
parameter real fc=0.5 from [0:1);
parameter real tau = 0 from [0:inf);
parameter real cgbo = 0 from [0:inf);
parameter real cgso = 0 from [0:inf);
parameter real cgdo = 0 from [0:inf);
parameter integer dev_type = `n_type;

`define EPS0          8.8541879239442001396789635e-12
`define EPS_OX          3.9*`EPS0/100.0

`define F1(m, f, v)     ((v/(1 - m))*(1 - pow((1 - f), m)))
`define F2(m, f)        (pow((1 - f), (1 + m)))
`define F3(m, f)        (1 - f*(1 + m))

   //
   // visible variables.
   //
   real vds,
      vgs,
      vbs,
      vbd,
      vgb,
      vgd,
      vth,
      id,
      ibs,
      ibd,
      qgb,
      qgs,
      qgd,
      qbd,
      qbs;

   real kp, fc1, fc2, fc3, fpb, leff;
   real beta;

   integer dev_type_sign;

   analog begin

      @ ( initial_step or initial_step("static") ) begin
         leff = length - 2*xj;
         kp = u0*`EPS_OX/tox;
         fc1 = `F1(mj, fc, vj);
         fc2 = `F2(mj, fc);
         fc3 = `F3(mj, fc);
         fpb = fc*mj;

         if( dev_type == `n_type )  dev_type_sign = 1;
         else dev_type_sign = -1;
      end

      vds = dev_type_sign*V(vdrain, vsource);
      vgs = dev_type_sign*V(vgate, vsource);
      vgb = dev_type_sign*V(vgate, vbody);
      vgd = dev_type_sign*V(vgate, vdrain);
      vbs = dev_type_sign*V(vbody, vsource);
      vbd = dev_type_sign*V(vbody, vdrain);

      if (vbs > 2*phi) begin
         vth = vto + gamma*sqrt(2*phi);
      end else begin
         vth = vto - gamma*(sqrt(2*phi - vbs) - sqrt(2*phi));
      end


      //
      // parasitic diodes...
      //
      ibd = is*(exp(vbd/$vt) - 1);
      ibs = is*(exp(vbs/$vt) - 1);

      if (vbd <= fpb) begin
         qbd = tau*ibd + cj*vj*(1 - pow((1 - vbd/vj), (1 - mj)))/(1 - mj);
      end else begin
         qbd = tau*ibd + cj*(fc1 + (1/fc2)*(fc3*(vbd - fpb) +
            (0.5*mj/vj)*(vbd*vbd - fpb*fpb)));
      end

      if (vbs <= fpb) begin
         qbs = tau*ibs + cj*vj*(1 - pow((1 - vbs/vj), (1 - mj)))/(1 - mj);
      end else begin
         qbs = tau*ibs + cj*(fc1 + (1/fc2)*(fc3*(vbs - fpb) +
            (0.5*mj/vj)*(vbs*vbs - fpb*fpb)));
      end

      //
      // channel component of drain current. (channel charge ignored)...
      //
      beta = kp*width/leff;
      if (vgs <= vth) begin
         id = 0;
      end else if (vgs > vth && vds < vgs - vth) begin

         //
         // linear region.
         //
         id = beta*(vgs - vth - vds/2)*vds*(1 + lambda*vds);   
      end else begin

         //
         // saturation region.
         //
         id = beta*0.5*(vgs - vth)*(vgs - vth)*(1 + lambda*vds);
      end

      qgb = cgbo * vgb;
      qgs = cgso * vgs;
      qgd = cgdo * vgd;

      I(vdrain, vsource) <+ dev_type_sign *  id;
      I(vbody, vdrain)   <+ dev_type_sign * (ibd + ddt(qbd));
      I(vbody, vsource)  <+ dev_type_sign * (ibs + ddt(qbs));
      I(vgate, vbody)    <+ dev_type_sign *  ddt(qgb);
      I(vgate, vsource)  <+ dev_type_sign *  ddt(qgs);
      I(vgate, vdrain)   <+ dev_type_sign *  ddt(qgd);
   end
endmodule