Cadence招聘前端设计工程师-FPGA/MMP

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Cadence招聘前端设计工程师-FPGA/MMP

Title: Lead DesignEngineer-FPGA

Location： SH

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Title: Lead FPGA Design Engineer

                                                         

Position Description:      

-Responsible for designing and developing sub-systems andmodules or components of hardware based verification products.

-In addition modifying, updating and productizing existinghardware based verification products. Perform as individual contributor on FPGAbased design projects involving board design, RTL design, verification,productizing and documentation.

-Work on diverse problems related to FPGA design, simulationor verification issues.

                                                         

Position Requirements:

-The position requires BSEE, or equivalent, with a minimumof 4 yrs of industry experience in designing hardware systems.

-Must have excellent communication skills, both written andverbal. Technical expertise in FPGA design for either Altera or Xilinx productsis required. Experience in FPGA design methodologies including high speeddesign, serial protocols and FPGA timing closure is desired.

-In addition RTL design knowledge using Verilog is requiredalong with experience in using RTL verification tools and flows. Verificationusing with Cadence simulation products is desired. -Experience with scriptinglanguages like Perl, TCL C-shell is strongly recommended. Experience with PCBtools is also desired.

Senior DesignEngineer--Memory Modeling Portfolio

Location： SH

Position Description:     

1.Responsible for scheduling, designing, developing, andsupporting IP models of system level memory such as SDRAM (LPDDR, HBM), NANDFlash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS models for use on hardwarebased verification products. Also responsible for updating, maintaining,documenting, and supporting existing system level memory model products.2.Perform as individual contributor for RTL design, verification, productizing,and documentation of memory IP. Interface with internal and external customersto work on diverse problems and solutions related to emulation, simulation, orverification. Perform as team member toward cross verification of and crosstraining in memory IP as well as in developing and using lifecycle processes toensure product quality.

PositionRequirements:

Essential:

1.The position requires BSEE, or equivalent, with a minimumof 4 yrs of industry experience in designing hardware systems.

2.Must have excellent communication skills with both writtenand spoken English. RTL design knowledge using Verilog/SystemVerilog isrequired along with experience using RTL verification tools and flows.

3.Debugging experience. Experience with team-wide collaborationtools and process. Drive and ability to schedule workload and plan own taskseffectively.

4.Strongly recommended: Verification experience usingCadence simulation and/or emulation products is highly desired. Programmingexperience with scripting languages like Perl, TCL, C-shell is stronglyrecommended.

5.Experience in memory sub-system design and operation isstrongly recommended.