马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册
x
Key responsibilities/duties: 1.
Top or block-level physical design. From post DFT netlist to gds. Finish all implementation job and signoff check. 2.
Make sure on schedule and qualified delivery. 3.
Make effective technical communication with customer on the design challenge, critical issues. 4.
Optimize the design flow according to the project requirement. 5.
Mentoring the new inexperienced engineers. Requirements (indicate “must” or “preferred”) Key skills & knowledge:
1.
Candidate should be familiar with sub-micron physical design methodologies. This includes floor planning, place and route, power analysis, timing closure, physical verification. 2.
Familiar with main stream place and route tools, timing analysis and physical verification tools is required. 3.
Proficiency in using Perl, TCL or other scripting languages is expected 4.
MSEE or BSEE with 4+ years of related experience is required. 5.
Experience with Cadence Place and Route tools is desired. Strong debugging and team work skills is essential. 有意向请联系:Chloe-zhang@kthr.com;微信号:13916933764 |