在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
查看: 1857|回复: 0

[招聘] Cadence招聘Principal Product Engineer- library characterization

[复制链接]
发表于 2016-3-21 17:41:02 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x

Cadence招聘Principal Product Engineer- library characterization

Location Shenzhen

更多职位信息敬请关注Cadence公众微信平台:Cadence微招聘

If you haveinterest, PLS send your update CV to job_china@cadence.com

Title: PrincipalProduct Engineer- library characterization

Position Description:   

We are looking for a dynamic individual to join the Cadencelibrary characterization development group. This group is currently developing the best-in-class librarycharacterization tools for standard cells, IO cells, memories and analog /mixed signal macros.  As a productengineer, you will shape our products and contribute to our marketsuccess.  The product engineering team isthe "voice of the customer" within the Characterization R&D groupand is responsible for communication between R&D and sales, marketing, andapplication engineering as well as interfacing directly with majorcustomers.  You will definespecifications for new characterization product features and help supportadvanced customer evaluations especially for new product roll-outs. You willwork together with R&D on implementation and development of customer testsuites. You will be responsible for reviewing product documentation, developingdemonstrations and training as well as writing application notes and technicalwhite papers.

PositionRequirements:

1.
BS plus 5+ years’ experience in Librarycharacterization with knowledge of Tcl, Shell Scripting (sh, csh, AWK etc.) andexcellent communication skills.  Detailedknowledge of Liberty ™ Library data formats (NLM, CCS and ECSM) and transistorlevel (spice) simulation is required for this position.  Familiarity with static timing analysis isdesired.  We prefer candidates withexperience in:

2.
Transistor circuit simulation and analysis usingSpectre, Finesim, and/or Hspice

3.
Memory simulation and analysis usingSpectre_XPS, Finesim_Pro and/or XA

4.
Static timing, signal integrity and poweranalysis tools (Tempus/ETS/Voltus/PrimeTime/PT-PX),

5.
Standard cell, and IO/IP characterization andvalidation

6.
Digital Design

7.
Mixed signal design with knowledge of VirtuosoADE

8.
Design and simulation of large mixed signalblocks such as PLL, SERDES, DAC, ADC.

9.
Memory design and characterization

10.
Statistical variation simulation and modeling(Monte Carlo analysis) including LVF and AOCV

您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /1 下一条

小黑屋| 手机版| 关于我们| 联系我们| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2025-7-15 18:12 , Processed in 0.012503 second(s), 7 queries , Gzip On, MemCached On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表