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C 设计(高级)工程师/经理
Responsibilities:
You will lead other Design Engineers in a team to meet the company's objectives. Design and implement digital communication system blocks and whole chip including specification trade-offs and optimization, micro-architecture, RTL coding, Synthesis, STA and simulation, chip testing and characterization. This is a full-time position with solid equity opportunity.
Qualifications Include:
5+ years of experience in Verilog/Synthesis-based ASIC/FPGA Design for mass production IC chipsExperience with project and team management
Experience from front-end to back-end (RTL, synthesis, verification, and test support) with data networking ASIC(SDH/SONET/POS/Ethernet, TCP/IP)
Verilog language and simulation verification experience
Familiar with TCL/Perl
Logic Synthesis and Static Timing Analysis
Interface with Place and Route and back-annotated simulation verification
Team-work spirit, and with a strong drive to excel
成都苏州两地均招聘
FPGA(高级)工程师:
职责描述:
1. 与市场和软件人员合作,参与评估客户需求和制定网络数据包处理板卡的设计方案
2. 负责FPGA的Specification和设计实现
3. 负责板卡的系统验证和联调,协助客户进行测试
职位要求:
1.有设计用于SDH/SONET/POS/Ethernet/IP数据包处理的FPGA的工作经验
2. 熟悉TCL/Perl脚本
3. 具有调试由FPGA、CPU 和ASIC组成的板卡的经验和能力。
3. 熟悉PCIe等接口设计
4. 良好的团队合作和敬业精神
5. 有数据网络通信系统设计经验者优先
成都苏州两地均招聘
如有意向请与 付女士联系 电话:0512-62727225 邮箱:fu.wenyan@xel-tech.com |
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