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Job Location: Shanghai 1. MSEE with 6+ years or Bachelor with 8+ years of industrial experience in ASIC design 2. 4+ years or more years of experience in physical design of deep submicron digital ASIC chips 3. Demonstrate strong leadership and work well with cross-functional teams 4. Good listening, writing and speaking English 5. Familiar with Back-End (physical design) EDA tools and hierarchical fullchip floorplan flow 6. Good at scripts or tcl 7. Plus with 3+ projects tapeout experience [url=mailto:有意者请将简历发送至zoe.yu@amd.com]有意者请将简历发送至zoe.yu@amd.com[/url]和nicole.yu@amd.com,标题请注明应聘职位。谢谢! |