Cadence高薪招聘ASIC Verification Engineer

yoceans

大家好，cadence目前急招一名ASIC Verification Engineer
待遇业界领先，如有意向请投：xfyang@cadence.com

Position Description:

1.Deliver/implement advancedverification solutions by utilizing Cadence’s Incisive Verification productportfolio. The engineer should be able to act as a strong team member andcontributor, leading team projects and initiatives. Exercise judgment within generallydefined practices and policies.

Specific duties include:

1. Deep understanding on ASICdesign and verification flow

2. Excellent knowledge of advancedverification methodology like eRM/OVM/UVM/VMM

3. Familiar with Cadence’sIncisive Plan to Closure Methodology (IPCM)

4. Proficiency in System Verilog,System C and/or e (Specman)

5. Developing and usingVerification Components (eVC,OVC,UVC,VIP)

6. Developing and using assertionbased verification and formal analysis methods

7. Skilled in scripting language,such as Perl,C shell, Python, Makefile

8. Assessing the projectverification requirements

Position Requirements:

Essential Qualifications:

1. BS degree with 4+ years ofapplicable experience, MS degree with 2+ years of applicable experience inelectrical engineering, microelectronics, comparable engineering science orsolid state physics.  

2. Essential that the individualdemonstrates strong communication, verbal and written. Requires goodcommunication skills in English.

Desirable Qualifications:

1. Will have demonstrated hands-onexperience and expertise with Cadence verification design tools or equivalenttools, flows and methodologies required to execute a verification project.

2. Will have demonstratedsuccessful completion of 3+ verification projects as an individual contributor

3. Will have DDR projectverification experience