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Job Location: Shanghai Responsibility:
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Understand the design spec ·
Develop test plan and write tests toverify system IP in IP level or SOC level ·
Work with RTL designers and others to debugthe failed tests ·
Run verification related flows and fixissues ·
Complete the verification target ateach milestone
Requirement:
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Master with 2+ (or Bachelor with 5+)years working experience in ASIC area ·
Solid experiences with simulation modelcreation and the testbench build ·
Excellent knowledge of designverification methodology, such as OVM/UVM, SystemVerilog ·
Advanced programming knowledge on C/C++,perl, Tcl/tk, Makefile ·
Familiar with Linux Environment ·
Candidate must have one or more of thefollowing experience/knowledge: 1) Micro-processor (e.g. ARM) architecture andperipheral; 2) Popular on-chip bus (AMBA/AXI) or NOC; 3) low power design andverification methodology; 4) Standard IO IPs, includingSPI/SMBUS/GPIO/I2C/I2S/UART; 5) DFT/JTAG, etc. ·
C/C++ software development experiencesis a plus ·
Verilog programming skill is a plus ·
Good communication skill and fluent English ·
Good team player and strong sense ofresponsibility ·
Strong problem solving skills
有意者请将简历发送至:zoe.yu@amd.com,标题请注明应聘职位。 |