Cadence上海2015年12月ICD后端部门招聘产品研发、产品测试、产品工程工程师和实习生

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Cadence上海2015年12月ICD后端部门招聘产品研发工程师、产品测试工程师、产品工程工程师和实习生如下：

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*** 产品研发1. Lead Software Engineer
Position Description:
 Responsible for developing and maintain physical verification engine in Innovussystems.
 Responsible for implementation for physical design rule check of advanced nodeprocess.
 Responsible for performance improvement in current physical verification engine.
Position Requirements:
 The candidate should be very strong at complex software development with C or C++on UNIX platform, domain knowledge at Physical Design Rule is preferred.
 The candidate will be responsible for development of complicated algorithms tocheck design rule violation among huge geometries, the experience to handle largedata manipulation is preferred.
 The candidate should have 3 years software development experience with MS orPHD degree of CS/EE/Math or others related.
 Good team player with strong written and verbal communication skills
 Familiar with LEF/DEF is preferred, and the ability to geometrical operation isdefinitely a plus.

2. Lead Software Engineer
Position Description:
 Responsible for designing, developing, troubleshooting and debugging poweranalysis software.
 Works on extremely complex problems where analysis of situations or data requiresan evaluation of intangible variance factors.
 Exercises independent judgment in developing methods, techniques, and evaluationcriterion for obtaining results.
 Work leadership may be provided by assigning work and resolving problems
Position Requirements:
 The candidate should have MS/PhD in EE/CS, strong programming skills in C++,and deep familiarity with object-oriented programming methods.
 Prior knowledge and experience with multi-threaded programming, numericalanalysis techniques, and in-depth understanding of VLSI chip power analysispreferred.

3. Lead Software Engineer-Database
Position Description:
 The candidate will be responsible for maintenance, development and improvementof a Cadence Database* (used by Innovus/Tempus/Voltus).
Position Requirement:
 MS above in CS/EE or similar level of expertise with 3+ years of workingexperience.
 Excellent programming skills in C/C++ on Linux/Unix platform, script (csh, Tcletc.) programming is a plus.
 Demonstrated problem-solving, architecture, algorithmic.
 Good team player with strong written and verbal communication skills.
 Strong desires to learn and explore new technologies.
 Multi-thread programming experience is a plus.
 EDA software development experience or IC design knowledge is a plus.

4. Lead Software Engineer-GUI
Position Description:
 The candidate will be responsible for the development of Voltus GUI in Cadence
Position Requirements:
 MS in Computer Science or related area with 3+ years of working experience orPHD.
 Programming skill on Linux/Unix platform is must.
 Being Familiar with GUI application development, such as Qt, tcl/tk, X Window.
 EDA software development experience or IC design knowledge is a plus, especiallyon power and rail analysis.
 Multiple thread programming experience is a plus.
 Strong desires to learn and explore new technologies and is able to demonstrate goodanalysis and problem solving skills
 Good English communication skill, both oral and written.

5. Principal Software Engineer-IPO
Position Description:
 The candidate will be a member of the Innovus IPO (in-place optimization) team inShanghai, to work on the development and maintenance of the IPO project.
Position Requirements:
 MS/PHD from EE, computer science, math or related.
 IC design knowledge is necessary, synthesis, static timing analysis, placementknowledge will be a strong plus.
 Advanced developing and debugging capacity in LINUX environment, familiar withC/C++, gdb etc
 Strong problem-solving, algorithmic capacity.
 Experience with script language, TCL is a plus.
 Fluent English in both oral and written.

6. Principal Software Engineer
Position Description:
 This software engineering position will support and improve the implementation thestate of art extraction products in a fast-paced, small team environment.
 We are looking for a highly motivated software engineer to work on the developmentnew applications for parasitic extraction.
 This person will be responsible for implementing new techniques, algorithms andlibrary API in C++.
Position Requirements:
 Strong algorithm background, programming skills and implementation in dealing andprocessing of large amount of data
 Good communication skills and desire to learn in a startup like environment
 Knowledge and experience with computational geometry, layout connectivity,parasitic extraction, capacitance modeling, FS development is a big plus
 Experience in C/C++ coding, with EDA physical verification or extractionbackground preferred
 Knowledge in UNIX shell and scripting language like TCL, Python, Perl
 Minimum of 3 years of software development experience with BS/CS degree

7. Lead Software Engineer-Floorplan
Position Description:
 The candidate will be a member of the Encounter floorplan team in Shanghai, to workon the development and maintenance of manual Floorplan project.
 The responsibilities include the develop of new features and products, and supportother teams in Encounter product lines.
 The candidate must be comfortable working with existing code as well as developingnew functionality to address new requirements, and be working closely withlocal/remote team members, and be also strong technical support to team.
Position Requirements:
 Candidate must be an expert in software engineering methods and committed to highquality of development work.
 The individual must be team-oriented, possess good communication skills, selfmotivated, able to work independently and working with a team from multipleremote sites.
 Candidate must be able to develop detailed technical specification as well as theability to scope efforts required.
 The candidate must be also smart to capture new EDA technologies, and switchamong different areas successfully.
 Advanced developing and debugging software in UNIX & LINUX environments,familiar with gnu c/c++, gdb etc..
 Strong problem-solving, architecture, algorithmic.
 Familiar with interpreted language such as TCL is a plus.
 Knowledge of Digital Physical Design flow such asFloorplan/Placement/Routing/CTS is a plus.

*** 产品测试
1. Product Validation Engineer II for GigaOpt
Position Description:This engineer will work in Encounter GPS (Global Physical Synthesis) productvalidation team. The responsibilities include:
 Assist in Cadence EDI development and validation
 Validate and maintain comprehensive GPS unit and flow test cases for EncounterDigital Implementation System.
 Develop test suites of the new features of EDI GPS function
Position Requirements:
 MS of EE/CS
 Digital IC design knowledge is necessary, statistic timing analysis knowledge is astrong plus
 Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus.
 Good communication in English and Chinese, good confidence and self-motivation.

2. Product Validation Engineer II
Position Description:
 This engineer will work in Encounter block implementation productvalidation team. The responsibilities include:
 Assist in Cadence EDI development and validation Validate and maintaincomprehensive unit and flow test cases for Encounter Digital ImplementationSystem.
 Develop test suites of the new features of EDI functions
Position Requirements:
 MS of EE/CS
 Digital IC design knowledge is necessary, statistic timing analysis knowledge is astrong plus
 Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus.
 Good communication in English and Chinese, good confidence and self-motivation.

3. Product Validation Engineer II
Position Description:
 This engineer will work in Encounter Router product validation team. Theresponsibilities include:
 Assist in Cadence EDI development and validation Validate and maintaincomprehensive Router unit and flow test cases for Encounter Digital implementationSystem.
 Develop test suites of the new features of EDI Router function
Position Requirements:
 MS of EE/CS
 Digital IC design knowledge is necessary, statistic timing analysis knowledge is astrong plus
 Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus.
 Good communication in English and Chinese, good confidence and self-motivation.

4. Product Validation Engineer II
Position Description:
 This PV engineer mainly works for advanced STA (Static Timing Analysis) andDelayCal features validation:
 Qualify delay calculation and timing analysis result in Innovus system;
 Maintain comprehensive regression suites for monitoring STA & delayCalstabilities;
 Upgrading regression cases to use advanced design node data and check the impact;
Position Requirements:
 Bachelor degree with 1~2 years working experience;
 Solid background knowledge in digital backend design, knowledge in STA ordelayCal is a strong plus;
 Be familiar with Linux system, and scripting skills with TCL or PERL or Shell;
 Patient, and good responsibility;
 Good communication in English and Chinese.

5. Lead Product Validation Engineer

Position Description:
 Cadence ICD Product Validation Regression system is the core system infrastructure of the whole Product Validation organization, which can greatly improve the wholeorganization's efficiency and boost the team productivity.
 This position is responsible for the regression system and application developmentand maintenance.
 The candidate need use all kinds of knowledge and skills to design and improve thesystem based on the business requirement for the organization operation and theexisting system and related software/hardware environment.
Detailed Responsibility:
 Analyze System and Business requirement, based on which design the system flowchart
 Do the needful system/scripts maintenance/improvement
 Communicate with related IT and PV team and drive to improve organizationoperation efficiency
 Innovate on the next generation system to boost organization's efficiency.
Position Requirements:
 Bachelor with 4 years related experience or Master with 2 years related experience
 Result driven and details focused working attitude
 Excellent analytical skills and complex system problem solving skills
 Strong technical experience in Unix/Linux usage
 Strong Perl/Tcl/Cshell scripting
 Good knowledge and experience in CGI programming
 Good knowledge in SQL database
 Knowledge in Web programing (JavaScript, php, Python, XML) is a strong plus
 Knowledge in NFS/Distributed Processing/Server Farm/Network is a strong plus
 Good written English and oral English is a strong plus.

6. Lead Product Validation Engineer for CLS
Position Description:
 Responsible for developing and implementing test methodologies, analyzing testdata and maintaining regression.
 Develop the automatic test system for Cadence products
 Work closely with a group of professionals in R&D, PE, and Software Release teamto enhance the quality of CLS(OPC) product.
Position Requirements:
 MS or above majored in EE or CS.
 Must have QPV experience, OPC related work experience is a plus.
 The related OPC tools experience is preferred.
 Shell/Perl programming skill.
 Candidate must have excellent ability to learn, explore and solve problems, haveteam-cooperating and innovating spirit.
 Candidate must possess good Chinese and English communication skills;

8. Lead PV Engineer -Sigrity and Allegro PCB SI
Position Description:
Introduction
 We are looking for a signal integrity engineer with 1-5 years of experience in HighSpeed design. You will be responsible for testing and overseeing the qualitymanagement of our family of software products that deal with SI design.
Duties
 You will work within a global multi-functional team to review project plans andfunctional specifications, develop test criteria and written test plans, manuallyexercise and test functionality of the Allegro PCB SI and Sigrity products anddevelop automated tests within the existing test environment. As this positionrequires a good understanding of the signal integrity knowledge. You will maintainregression tests and evaluate results on a regular basis.
Position Requirements:
Requirements
 BS Degree is required, MS is preferred
 Working experience with the Sigrity tools is strongly desired
 Solid understanding of the following: signal integrity, modeling and simulation
 Recent experience with signal integrity tool is a must
 Knowledge of other PCB design, routing, and packaging is a plus
Experience
 Knowledge of Windows and Linux platforms is essential
 Any experience in software validation
 Programming knowledge in Perl is strongly desired
 Experience with an error tracking and reporting product is valuable
Basic Abilities
 Strong written and verbal communication skills, in English and Chinese aremandatory as the candidate will be interacting with a global team based in the USand China.
 Ability to follow a schedule is essential
 Familiarity with software development life cycle is a plus
 Ability to detect, report and explain defects effectively is crucial
 Possess good analytical, problem solving skills
 Understand test processes and methodologies in a software developmentenvironment
 Self-starter, self-sufficient, able to work independently as well as with teams, able tomultitask

*** 产品工程
1. Product Engineer II

Position Description:
 The primary responsibility is designing, developing, troubleshooting and debuggingsoftware programs on Unix/Linux platforms.
 Will be involved in developing software tools for advanced chip design platforms.
 The responsibilities also include engaging with customers in understanding theirASIC design requirements for nano-technology process nodes and assisting them inadopting Cadence design platform and helping them in performing successfultapeouts of their System-on-chip designs using the same.
 The job will also involves presenting and demonstrating relevant Cadencetechnologies and carrying out product evaluations, workshops, trainings andcompetitive replacement campaigns.
Position Requirements:
 The candidates should have strong in-depth P&R design experience in COT or ASICarea.
 Experience and ability to get solutions in Floor plan, Power Planning/Analysis, CTS,timing optimization/analysis, signal integrity and DFM issues (DRC & Antenna) is aMUST. Strong interest and understanding of design methodologies are required.
 Need to have good knowledge on VDSM (40nm and below) processes issues.
 Good verbal and written presentation are must.
 Hands-on Cadence Encounter experience is a big plus.
 Minimum master degrees in EE or CS.

2. Principal Customer Engagement Engineer

Position Description:
 The Customer Engagement Product Engineer plays a key role in defining, validating
and deploying Cadence’s front end solutions while working with key customers.
 This position requires highly technical engineers with great communication skills anda strong desire for working with customers, developers, marketing and sales.Candidates must be passionate about adopting and promoting new technologies andmaking customers successful.
Position Requirements:
 Understanding of system design and logic design using an HDL language
 Understanding of logic and physical synthesis and formal verification EDAtools/flows
 Ability to work with customers directly to understand and address requirements
 Manage and conduct deployment activities including integration into customer’sflows
 Ability to develop and deliver product presentations and product demos to highlightand position technical features and capabilities
 Develop and deliver technical field training as part of product deployment strategy
 Ability to represent customer’s viewpoint and provide feedback on tools and flows toR&D
Experience:
 Expertise in IC design and knowledge in Verilog/VHDL, and scripting (TCL, shell)languages is a requirement
 Experience with logic and physical synthesis/verification of complex chips is arequirement
 Experience with Cadence physical design and implementation tools is desired
 Experience with Cadence formal verification tools and methodologies is desired
 Strong organization, presentation, and debugging skills are a requirement, as is theability to handle multiple simultaneous projects successfully
 Previous field applications, consulting, or experience with customer interfacing isrequired
Language:
 Good command of the English language, both written and spoken – Required
Travel:
 On average 5-10% travel is to be expected, mostly within the country/region
Education:
 The person should possess the BS/BE level of understanding of CS or EEEngineering concepts
 Minimum Education Required: education level of BS with 7+ years’ experience (orMS with 5+ or more years of experience).
Working Model
 This position reports into the Customer Engagement Group. On average, the balancebetween local and international activities and between customer facing and internalactivities is as follows:
 75% local top accounts
 15% Product Engineering tasks including deployment enablement
 10% international top accounts

3. Lead Product Engineer

Position Description:
 Responsible for product engineering and direct customer support of CadenceSpeedBridge hardware products.
 Responsible for the creation, deployment and debug of protocol based solutions forPCIE, USB, SATA and other protocols.
 Perform as individual contributor on emulation and FPGA based design projectsinvolving productizing, support, design, verification, training and documentation.
 Work on moderately complex problems related to emulation and FPGA emulation,design, simulation or verification issues.
Position Requirements:
 The position requires BSEE, or equivalent, with a minimum of 2 yr of industryexperience in hardware systems.
 Must have excellent communication skills, both written and verbal.
 Experience in FPGA design for either Altera or Xilinx products is desired.
 RTL design experience using Verilog is required along with experience in using RTLverification tools and flows.
 Verification using with Cadence simulation and emulation products is desired.
 Experience with scripting languages like Perl, TCL C-shell is desired.

4. Lead Product Engineer

Position Description:
 Work in shanghai Silicon Signoff and Verification (SSV) electrical PE team, focus onVoltus Power System (Voltus).
 Support key customer engagements and local AEs to help on the business increase.
 Working as a domain expert to well communicate with customers for their valuablefeedbacks
 Co-work closely with R&D team to enhance the tool based on customers' realdemanding
Position Requirements:
 Master with 3-6 years working experience or Bachelor with about 5-8 years’experience.
 Electrical analysis experience is necessary, IC level or system level power relatedanalysis will be desired, e.g. Cadence Power System, Redhawk, Totem, Sigrity.
 Working experience with foundry and process tech files, spice models are desired
 Product Engineering and customer supporting experience is desired.
 Good communication in English and Chinese, good confidence and good selfmotivation.

5. Principal Solutions Engineer, HSV R&D

Position Description:This position is for HSV SWAT team. SWAT team belongs to HSV RD, and is incharge of:
 Support: support the key account and key engagement in the local area that teammember is located.
 Explore: explore user's need and take the feedback back to BU
 Validate: Validate and deploy the new technology on site, including the knowledgetransfer to local team
 The focus on the technical aspects includes:
 Cadence HW Acceleration Platforms and related solution especially SW HW coverification and system level verification
 Cadence Acceleration Verification IP portfolio
 HSV product integration with other Cadence products such as Incisive Simulationand RTL Compiler for power analysis
Position Requirements:
 SW HW Co-verification, means either the RTL design and verification knowledge, orthe experience of firmware, OS, driver development in IC design firms.
 A good knowledge of RTL design and verification tools (HDLs, synthesis tools,design simulation, acceleration using emulators) or the firmware development tools.
 Good understand on the challenge of SoC verification
 ESL knowledge is a very great plus
 Previous knowledge and hands on experience of emulation project is a great plus
 System Verilog and UMV methodology is a great plus
 Knowledge of at least one popular script language such as, Perl, Shell, Tcl, or C
 Ideally the person should possess the BS/BE level of understanding of EEEngineering concepts
 Minimum Education Required: education level of BS with 10+ years’ experience (or
MS with 7+ or more years’ experience).


*** 实习生

1. R&D Intern- Placement

Position Description:
 This intern will work in Encounter placement team for project development andanalysis.
Position Requirements:
 EE/CS MS or PH.D, good at C/C++ programming.
 Could understand the concept of EDA backend design, especially placement.
 Strong mathematics background: non-linear optimization is a plus.
 Good communication in English and Chinese, good confidence and good selfmotivation.

2. Intern - Software Engineering for power route

Position Description:
 This position is for a R&D engineer to assist in development and analysis of powerroute.
Position Requirements
 The candidates should have strong software programming skill with C/C++ onLinux/Unix platform.
 Strong desires to learn and explore new technologies and is able to demonstrate goodanalysis and problem solving skills
 Good communication in English and Chinese, good confidence and good selfmotivation.

3. Intern-Product Validation for flow QOR

Position Description:
 Do flow QOR review, debugging timing, DRC, memory and TAT issues underhelp of project leader.
 Write some scripts to improve efficiency
 Do data collection and analysis
 Co-work with team members to accomplish different projects
Position Requirements:
 MS or excellent undergraduate
 Digital IC design knowledge is necessary, statistic timing analysis knowledge is astrong plus
 Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus.
 Good communication in English and Chinese, good confidence and self-motivation.
 Commitment to work as intern for at least 6 months.

4. Intern-Product Validation for NanoRoute

Position Description:
 This intern will work in Encounter Block Implementation Product Validation teamand focus on NanoRoute. The responsibilities include:
 Assist in Cadence EDI flow development and validation
 Validate and maintain comprehensive NanoRoute unit and flow test cases forEncounter Digital implementation System.
 Develop test suites of the new features of EDI GPS functions.
Position Requirements:
 MS or excellent undergraduate
 Digital IC design knowledge is necessary, statistic timing analysis knowledge is astrong plus
 Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus.
 Good communication in English and Chinese, good confidence and self-motivation.
 Commitment to work as intern for at least 6 months

5. Intern-Product Validation

Position Description:
 Assist in Cadence hierarchical and DB areas development and validation
 Validate and maintain comprehensive hierarchical/Database unit and flow test casesfor Encounter Digital implementation System.
 Develop test suites of the new features of hierarchical and Database functional/flowsolution.
Position Requirements:
 MS or excellent undergraduate
 Digital IC design knowledge is necessary, statistic timing analysis knowledge is astrong plus
 Unix System knowledge, vi/TCL/TK/CSH/Perl will be plus.
 Good communication in English and Chinese, good confidence and self-motivation.

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