【NVIDIA社招】前端验证工程师（ASIC Verification）-上海

NVHR

Hi All,

这边是NVIDIA HR Tracy, ASIC Design/Verification Engineer (Clock), 具体职位描述如下，有意向的朋友，欢迎发送简历到 tracyw@nvidia.com   
QQ: 1751315121

收到简历 我会及时同你联系； 谢谢；工作经验2-5年
工作地点: 上海市浦东新区 秋月路26号 （靠近地铁2号线 广兰路站）


公司介绍
http://www.nvidia.cn/object/about-nvidia-cn.html
在二十年的时间里，NVIDIA 一直在视觉计算方面 (计算机图形的艺术与科学) 勇当先锋。
凭借我们发明的 GPU ——现代视觉计算的引擎，这一领域现已扩张到涵盖了视频游戏、电影制作、产品设计、医学诊断以及科学研究等等。
现在，视觉计算正变得越来越重要，它影响着人们与科技之间的互动方式。

Position Title:        ASIC Design/Verification Engineer (Clock)
The NVIDIA Clocks group is looking for a top ASIC engineer with extensive experience in high-speed logic design and verification. The complexity of clocking structure has grown substantially in order to support high frequency clock domains. Modern clocking design needs to balance high frequency clocks with power, DFT, noise, circuit and physical design constraints.
Responsibilities:
- Design new clocks modules in order to support high frequency clock with all the above  constraints.
- Verify clock design with the industry standard tools and methods at unit and system level to deliver high quality clock modules.
- Ability to design novel techniques to distribute clocks over long distances with low insertion delay, skew and OCV effects.
- Perform STA on the designed clock modules.

MINIMUM REQUIREMENTS:
-BS / MS in electrical / computer engineering and related.
-Understand frontend ASIC design flow including RTL design, synthesis and timing analysis
-Familiar with verification methodology, tools and flow
-Strong programming skills in Perel and C/C++ is a plus
Excellent analytical and problem solving skills
-Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus
-Fluent English (both written and spoken) and excellent communication skills
-Ability to interface with many groups,  easy to cooperate with team membersBest Regards

祝好
Tracy

NVHR

顶！！！！！！！！！！

NVHR

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