Cadence 招聘数字前端+数字后端设计工程师

kengteng

Cadence SH 招聘 ：
1.Principal/Lead/Senior Physical Design Engineer-数字后端
                  2. Lead/Senior Design Engineer -(数字前端设计)
                  3. Lead/Senior Design Engineer -STA (数字前端设计)

更多职位信息敬请关注Cadence公众微信平台：Cadence微招聘

If you have interest, PLS send your update CV to job_china@cadence.com(简历投递格式：姓名+学校+申请职位)

职位信息：

1.Title: Lead/Senior Physical Design Engineer

Position Description:     
1. Focus on high speed digital DDR and HBM IP physical implementation
2. Have good physical design experiences in the digital implementation domain including Floorplan, P&R, Physical verification, DFM.
3. Have a solid background in circuits, electronics & physics & should be very willing to learn new technology for advance node and design methodology
4. Skilled in scripting language, such as Perl, C shell, Makefile
5. Feeling responsible for technical delivery, good team played, design quality/schedule focus                                                      
Position Requirements:
1. Essential Qualifications: Have MS degree with 2 ~4+ years of applicable experience, MS degree with 4 ~ 6+years of applicable experience in electrical engineering, microelectronics.
2. Essential that the individual demonstrates strong communication skill
3. Requires good communication skills in English.

2. Title: Lead/Senior Design Engineer (数字前端设计)
Job location: Shanghai/Beijing
Position Description:
Deliver/implement DDR IP. The engineer should be able to act as a strong team member and contributor, leading team projects and initiatives. Exercise judgment within generally defined practices and policies.

Specific duties include:
- Be responsible for building and leading a high-performance IC design team, owning the IC micro-architecture, package and test platform development, refining the EDA design flow
- Proficiency in logic design, simulation, synthesis, STA and testing
- Proficiency in Verilog and its simulation environment
- Good knowledge of IC design
* At least five years  experience driving complex IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.

Position Requirements:
1. Essential Qualifications: Must have BS degree with 6+ years of applicable experience, MS degree with 4+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
2. Essential that the individual demonstrates strong communication, verbal and written. 3. Requires good communication skills in English.

3.Title: Lead/Senior Design Engineer -STA (数字前端设计)
Location: SH
Position Description:
Deliver/implement DDR/HBM IP. The engineer should be able to act as a strong team member and contributor. Exercise judgment within generally defined practices and policies.
Specific duties include:
1.Proficiency in logic design, simulation, synthesis, STA and testing
2.Proficiency in Verilog and its simulation environment
3.Good knowledge of IC design
4.At least two years’ experience driving complex IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.
Position Requirements:
1. Essential Qualifications: Must have BS degree with 4+ years of applicable experience, MS degree with 2+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
2. Essential that the individual demonstrates strong communication, verbal and written.
Requires good communication skills in English.
Desirable Qualifications:
1.Will have demonstrated successful completion of 5+ design projects as an individual contributor
2.Familiar with JEDEC-DDR/HBM, DFI and AMBA protocols and have DDR project design experience