Cadence招聘数字前端设计

kengteng

Cadence招聘 Lead/Senior Design Engineer (数字前端设计)

Joblocation: Shanghai/Beijing

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PositionDescription:

Deliver/implement DDR IP. Theengineer should be able to act as a strong team member and contributor, leadingteam projects and initiatives. Exercise judgment within generally definedpractices and policies.

Specificduties include:

- Be responsible for buildingand leading a high-performance IC design team, owning the ICmicro-architecture, package and test platform development, refining the EDAdesign flow

- Proficiency in logic design,simulation, synthesis, STA and testing

- Proficiency in Verilog andits simulation environment

- Good knowledge of IC design

* At least five yearsexperience driving complex IC development projects, excellent communicationskills and the uncanny ability to both lead and contribute in a cooperativeteam environment.

  

PositionRequirements:

1. Essential Qualifications:Must have BS degree with 6+ years of applicable experience, MS degree with 4+years of applicable experience in electrical engineering, microelectronics,comparable engineering science or solid state physics.

2. Essential that theindividual demonstrates strong communication, verbal and written. 3. Requiresgood communication skills in English.