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本帖最后由 synopsys_hire 于 2015-11-10 13:44 编辑
Job Title:Analog layout engineer
Location:Wuhan
Email: qyzhong@synopsys.com
Requirements:
You must be experienced with physical layout and verification tools such as Virtuoso , Laker, Calibre, Hercules.
You need have layout design experience for advanced process node like 40nm, 28nm.
You also need to have experience at least one of the following key functions: PLLs, High speed transmitters and receivers, High speed ADC, DAC and Bandgaps. Familiar with Unix and Windows operating system for script writing or post-processing.
Have excellent interpersonal and communication skills.
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